4 位超前进位加法器的设计

用verilog编写的lms算法。可实现自适应滤波功能(Lms algorithm written in verilog. Adaptive filtering can be achieved)

PCI arbi verilog source code

VHDL语言实现两个人掷骰子游戏，最多6次，大者胜则结束游戏并在点阵上显示，一直平手则一直进行直到达到6次。(Achieving the dice game between two people by using VHDL language.The maximum number of times is 6.The game will over when there is a biger one in one time,otherwise,the game will continue until the time of the game is up to 6.)

写一个单周期处理器运行一段mips指令，并包含mips指令转汇编码的程序(Write a single cycle processor to run a section of MIPS instruction)

4 级流水方式的8 位全加器。。。。。。(Way flow of 4 full adder 8. . . . . .)

This source is used to control 7 segments on FPGA boad

用verilog实现的UDP协议，包括arp，udp，ip分段协议等，对于想用FPGA实现TCP/IP协议的人来说，应该会起到一定的帮助作用(Implemented with verilog UDP protocols, including arp, udp, ip fragmentation protocol, etc., who want to achieve TCP/IP protocol with the FPGA people, should play a helpful role)

说明：  通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic communication )

本书介绍基于FPGA实现数字信号处理的原理与方法，作为Xilinx公司相关课程的培训教材(The FPGA implementation of DSP principle & method.)

特权同学主讲的FPGA设计的时序约束专题（STA部分）(Speaker privileged classmates timing constraints for FPGA design topics (STA section))