xilinx zc706开发板Verilog流水灯源代码

Lab view using FPGA traing on lcd pannel

cordic 算法知道正弦和余弦值，求反正切，即角度。(The CORDIC algorithm knows sine and cosine values and asks for inverse tangent, that is, angle.)

LDPC码不同码长对比。码率选择1/2.码长分别为256，512，1024.(LDPC codes of different code length contrast. Bitrate select 1/2 yards long were 256,512,1024.)

说明：  基于FPGA的QPSK系统仿真及验证，硬件部分。(Simulation and verification of QPSK system based on FPGA)

我在这方面没有经验verilog.now公司我在做iq解调器项目。所以请提供解调器的verilog代码项目.iq解调器项目包括射频数据、混频器、低通滤波器、同相分量I、正交分量Q。

ALU 设计和验证平台的但在平台与监控、 检查器、 音序器、 驱动程序和接口

基于DE2-115的数字时钟 1.液晶显示，数码管显示 2.整点报时 3.闹钟 4.设置时间 5.设置闹钟(Digital clock based on DE2-115 1. LCD display, digital tube display 2. whole point 3. alarm clock 4. setting time 5. set the alarm clock)

vs自定义插件开发,带卸载功能,经测试完全可用，分享给大家，可以学习！(vs custom plug-in development, with the uninstall feature, has been tested and is fully available for everyone to share, you can learn!)

yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)

基于LabVIEW FPGA的频谱估计与分析(the power spectrum estimation and analysis based on LabVIEW FPGA)