clock for spartan 3 evaluatoin board

中文版DLX流水线技术相关方面介绍以及简单应用 适用于面对初学者讲解(Chinese version of the DLX pipeline technology-related aspects of introduction and a simple application Suitable for beginners to explain face)

用VHDL语言写了个FLAPPY_BIRD的程序，利用板子与屏幕可以运行游戏(VHDL language to write a program FLAPPY_BIRD by the board and the screen can run the game)

C语言写得FIR滤波器代码，简单实用，是学习滤波器设计的好材料，附带PPT滤波器设计说明(C language written FIR filter code, simple and practical, is a good learning materials of filter design, with PPT filter design )

9针的rs232与fpga之间的串口通信源程序(Rs232 9 pin serial communication with the source between fpga)

HDB3码在matlab中的仿真，包括原始码、AMI码及HDB码的相关仿真图形(HDB simulink in matlab)

说明：  ADV7179芯片的驱动程序，基于FPGA硬件实现，已经验证可以使用(ADV7179 chip drivers, FPGA-based hardware implementation has been verified using)

用Verilog代码实现的乒乓操作，用Verilog代码实现的乒乓操作(Verilog pingpong)

说明：  串口！ 这是一个使用的通信程序 ， 非常好用。(serial port Serial port! This is a communication program used, very useful.)

这是一个在FPGA上实现CRC算法的程序，包含了CRC-8,CRC-12,CRC-16,CRC-CCIT,CRC-32一共五种校验形式。-err

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License