Circular_Buffer，流水线型多位缓存器，verilog语言描述。通过modelsim 6。0仿真，quartus 综合通过。...

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

可综合的Verilog语法（剑桥大学，影印）.(A comprehensive Verilog Grammar (University of Cambridge, photocopy).)

System Generator环境中颜色空间转换建模(Color space conversion model in the System Generator)

MATLAB Filter Design HDL Coder Simunlink HDL Coder Xilinx ISE Webpack

原创，帧同步器的Verilog代码，在FPGA上验证实现过，无误。作为通信系统帧传输的仿真，有限状态机同步态和失步态的切换仿真。(Original Verilog code for frame synchronization, verify the implementation on the FPGA, and correct. Frame transmission as the communication system simulation, finite state machine synchronous state and the loss of the switching simulation of gait.)

用来检查FPGA通过PHY发送数据时是否有掉帧的现象(FPGA is used to check whether the PHY sends the data out of the frame with the phenomenon of)

基于VHDL语言的3级序列的产生，可以循环产生周期为7的m序列 -Based on the VHDL language for selecting the three sequences, you can have a cycle for cycle 7 m sequence

Efficient CIC filter Implementation using VHDL

用vhdl语言 来实现 四位并行加法器的功能 是本科生的必学内容-Using VHDL language to realize four parallel adder function is a must for learning the content of undergraduate

verilog开发FPGA，实现RS485串口通信(RS485 driver for FPGA )