RS232 data transmitter, suitable for beginners VHDL reference

在八位七段数码显示管上显示8位学号，要显示的学号可以在程序内改，经设备验证无错误，且运行良好。

他延误用户inrandom经历过或基于竞争的MAC方案是无界;用户可能需要等待论坛很长一段时间，直到他/她发送一些数据的机会。在otherhand，通过根据一定的deterministicpattern，这被称为由梅西和马特仕协议序列调度所述数据分组，延迟的hardguarantee可以完成。

绝对位置编码器biss与FPGA之间的通信(Absolute position encoder biss communication with FPGA)

6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard

it contains pdf file which has vhdl program of uart (universal asynchoronus receiver and transmitter). which very simple and easy to understand

说明：  CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。(CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write registers, read and write memory and execution.)

very nice program that i ensure anyone can use easily and will be efficient for hard project of elevator

LCD SpartaN3E fpga vi

Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.-Clock_Dithering_Verilog this is a Clock u_dither, everybody want to make Verilog-jitter can refer to.

JOP内核字节码获取，很难找的东东，呕血之作-JOP core byte code access, it is difficult to find the price. Zhi for hematemesis