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FPGA控制AD7321的模块
FPGA控制AD7321的模块,是本人亲自试验过的。有Verilog源码,和简单文档(Fpga control module of ad 7321, is I personally tested. Verilog source code, and simple documentation)
- 2018-01-31 20:04:27下载
- 积分:1
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SDI_test
stratixIVGX,芯片4sgx230es,SDI测试完整工程,实现SDI的收发(stratixIVGX,SDI Receive and Transmit)
- 2011-12-12 14:57:53下载
- 积分:1
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test2
说明: 试用Verilog HDL语言,设计十进制计数器,将计数过程用一个数码管进行显示(0~9)。要求首先使用Modelsim软件进行功能仿真,然后使用Quartus软件综合,并下载到开发板进行电路功能测试。(Using Verilog HDL language, a decimal counter is designed. The counting process is displayed by a digital tube (0 ~ 9). It is required to first use Modelsim software for functional simulation, then use quartus software for synthesis, and download to the development board for circuit functional test.)
- 2020-05-17 11:07:28下载
- 积分:1
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CIC
Efficient CIC filter Implementation using VHDL
- 2010-11-19 08:54:23下载
- 积分:1
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fir48
48阶FIR滤波器的verilog,包含测试文件(48-order FIR filter verilog, including test paper)
- 2021-04-14 19:58:55下载
- 积分:1
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DDS
Verilog实现DDS线性调频,Verilog实现DDS线性调频(Verilog implementation of DDS linear FM,Verilog implementation of DDS linear FM)
- 2015-07-29 19:59:36下载
- 积分:1
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liyuanlnx_IP_PLL
FPGA锁相环实验:
顶层文件加底层IP文件构成
top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)
- 2020-06-22 04:00:01下载
- 积分:1
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EDAshiyan2s
通过上翻键和下翻键来设置方波信号正负脉冲宽度,利用一排流水灯来显示按键的次数,通过观察流水灯亮的盏数确定占空比(按一次上翻键亮一盏灯,流水灯全亮时占空比调到了最高或者是最低状态,按一次下翻键灭一盏灯,流水灯全灭时占空比调到了最低或者是最高状态)。(Duty cycle of LED lights and adjustable oscilloscope display code)
- 2015-01-06 21:10:09下载
- 积分:1
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quartus环境下开发的三人表决器(三种不同的描述方式)maxplusII兼容...
quartus环境下开发的三人表决器(三种不同的描述方式)maxplusII兼容
- 2022-06-27 14:06:35下载
- 积分:1
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water_light
Verilog语言的流水灯设计程序,对初学者很有用。(Water lights Verilog language design program useful for beginners.)
- 2015-03-15 13:48:43下载
- 积分:1