DE2板实现的带有记忆功能的秒表

用PrimeTime的技巧，解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)

基于FPGA实现DSP与Rapid-IO网络互联()

实现自然对数运算的cordic算法的matlab浮点仿真，以及针对FPGA硬件平台的定点仿真测试(Achieve natural logarithm of cordic algorithm matlab floating point emulation, and FPGA hardware platform for fixed-point simulation testing)

应用背景此代码是移行为模型和添加乘数随着乘数和被乘数参数比特宽度关键技术Verilog 2001和Xilinx的Spartan 6 FPGA板试验台

CSS配合jquery制作完美漂亮的时钟，貌似在IE8下时钟不能获取时间啊！支持ie9、chrome、safari、firefox、opera （Chrome显示效果最佳，IE9下时钟无法工作）日历和骰子是原创，CSS3时钟并非原创但经过改良支持opera。数字日历的兼容性不错，圆形时钟就差点了，也希望一起交流，共同改进。(CSS with the jquery make perfect beautiful clock, seemingly in IE8 under the clock can not get the time ah! Support ie9, chrome, safari, firefox, opera (Chrome show the best results, the clock does not work under IE9) calendar and dice is original, CSS3 clock is not original but after improved support opera. Digital calendar compatibility is good, almost round the clock on, and also hope together, and work together to improve.)

按键控制数码管  八位数码管  控制0到9  共阴极数码管

FIR滤波器Verilog实现代码，买的开发板教程里的，亲测可用！

this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga

自编的64B/66B解码程序，做毕业设计的时候写的。(The decoding process 64B/66B , written when i am in the school。)

实现AHB转SRAM接口实现，支持猝发，零等待延迟(Implementation of AHB to SRAM Interface)