基于Nios II checksum利用 altera的验证C2H accelerator的系统-Cyclone II

这包括地址数据总线 （ad 总线） 的 verilog 代码为一个 cpu。地址数据位为 16 位。

基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)

完整的OFDM仿真程序，包括QPSK,16QAM调制，基于MATLAB，各个步骤都有详细的说明。(OFDM simulation program, based on the complete MATLAB, every step is described in detail.)

DAC0832的Verilog代码，适用于与ADC0809同时学习，效果明显！(DAC0832 Verilog code, applicable at the same time with ADC0809 learning, the effect is obvious!)

来自于NIOSII的那些事，该书详细地介绍了NIOSS的使用过程，非常适合初学者。(From the NIOSII those things, the book are detailed in this paper NIOSS use process, very suitable for beginners. )

Matlab agc ʵ

In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder. Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read the output or input 576 frequency lines.(This folder contains three directories: Huffman, IMDCT and Filterbank, each of them includes all the VHDL source codes of the component.)

verilog 有符号数 乘法器模块(verilog signed multiplyer)

接口模块，通过对高位地址的编码可实现在一个FPGA中配置四个独立的功能模块，每个功能模块具有一个带FIFO的输出口和13个独立的可由DSP读写的寄存器，寄存器功能可自定义。模块还包含两个全局寄存器，可实现全局复位，中断等功能。该模块以应用于实际的项目中，目前运行良好(FPGA to emif)

ISE Design Suite Software Manuals and Help - PDF Collection,ISE 软件手册以及帮助。(ISE Design Suite Software Manuals and Help- PDF Collection, ISE software manuals as well as help.)