同步清零复位的D触发器

SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。(This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1.)

说明：  vhdl code for full adder

本设计是基于FPGA设计一个地铁自动售票系统。 本设计采用自顶向下的模块化设计方法，基于FPGA使用VHDL语言设计制作一个地铁自动售票控制系统，该系统能出售2条线路3种不同价位的票，完成售票、找零、显示等功能。(The design is based FPGA design of a subway ticket vending system. This design uses a top-down, modular design method, a subway ticket vending control system based on FPGA using VHDL language design, the system can sell two lines of different priced tickets, complete the ticket, give change, display and other functions .)

串行流水线格式:使用COrdic 算法计算反正切:向量模式下求角度 16bit :数据全部补码格式 (Serial line format: Use COrdic algorithm arctangent: seeking angle vector mode 16bit: full complement data format)

代码用两种方法设计了一个基于多相滤波的内插器，低通滤波器采用128阶凯撒窗，内插倍数32，并且给定信号范围，验证了内插器的正确性，画出了内插前后信号的频谱。(The code design the interpolator based on polyphase filter using two methods.The low pass filter is 128 order Caesar window and interpolation multiple is 32.I give the range of the signal to verify the interpolator and plot the spectrum of the signal before and after the interpolator. )

ad7705通过spi时序进行读写，通过fpga模拟spi时序对adc进行读写，首先写入通信寄存器20h，时钟寄存器0C，通信寄存器10，设置寄存器40H，然后写通信寄存器进行读取。

调试bcm5396，写入和读取内部寄存器功能。功能验证可以用(Debug bcm5396, write and read the internal register function. Functional validation can be used)

Verilog 实验代码。。。经典的，里面都是完整的项目文件。 ISE环境。(Verilog test code. . . Classic, which is a complete project file. ISE environment.)

说明：  可以进行连续uart串口读写999次以上不出错，已经检测成功(It can read and write serial UArt more than 999 times without error. It has been detected successfully.)

说明：  16位右移位寄存器 下面描述的是一个位宽为16位的右移位寄存器，实际具有环形移位的功能，是在右移位寄存器的基础上将最低位的输出端接到最高位的输入端构成的。其功能为当时钟上升沿到达时，输入信号的最低位移位到最高位，其余各位依次向右移动一位。(16-bit right shift register The following description is a right shift register with a bit width of 16 bits. It actually has the function of circular shift. It is based on the right shift register, which connects the lowest bit output terminal to the highest bit input terminal. Its function is that when the rising edge of the clock arrives, the lowest displacement of the input signal reaches the highest position, and the rest of you move one bit to the right in turn.)