用Verilog HDL实现的uart通用串口通信程序，已经验证成功

针对QUARTUS的DMA的VHDL代码实现(DMA Controller Code in VHDL)

高速FIFO，verilog设计。速度高达130Mhz(High-speed FIFO, verilog design. Speed up to 130MHz)

It is the FSM implemented in Xylinx 14.7 on FPGA

利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)

module example_3_1(A, B, C, D, E);        output D, E;    input  A, B, C;    wire   w1;    and G1(w1, A, B);    not G2(E, C);    or  G3(D, w1, E); endmodule

手把手教你学FPGA 仿真篇,简单实用。(Hand in hand teach you to learn FPGA simulation, simple and practical.)

Diagram and how-to-make instructions pack of 6 diferent Amplifiers

共两个文件，一个是对网络芯片W5500进行控制的master spi接口，另一个是w5500命令控制逻辑，命令格式按照w5500芯片的要求，分为地址段，控制段和数据段进行统一控制。此外提供w5500芯片初始化及读写控制流程图。(A total of two documents, one is the master SPI interface for network control chip W5500, the other is a w5500 command control logic, command format in accordance with the requirement of w5500 chip, divided into address segment, unified control and data segments. In addition to provide w5500 chip initialization and read and write control flow chart.)

bt1120设计方案，描述了具体的方案设计以及整体的架构设计(Bt1120 design scheme, describes the specific scheme design and the overall architectural design)

该程序描述了运用FPGA进行控制的S形曲线和其他传统加减速控制曲线方法的控制曲线比较研究。(This program is compiled in matlab circumstance。Describing the approach of S-curve control method in FPGA in machine controlling.)