用Verilog HDL实现的uart通用串口通信程序，已经验证成功

硬件描述语言HDL(Hardware Description Language)经典教程(Classic Verilog tutorials)

1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core manual 7.2 5.verilog to achieve serial transmission)

忆阻器的PSPICE仿真，是忆阻器的宏模型，适合于cadence16.5版本(memristor PSPICE simulation)

DDR SDRAM控制器verilog代码及中文说明文档(DDR SDRAM Controller Using Virtex-5 FPGA Devices)

说明：  ldpc的算法介绍及其fpga上硬件实现(Introduction of LDPC algorithm and Its FPGA implementation)

SOPC系统的I2C代码 直接可用，可作为ＩＰ核用到自己的系统中(SOPC system I2C code directly available, can be used as an IP core in your system)

FPGA 与ad70676之间用并口通信 八个通道采集到的电压用串口打印出来(Parallel communication between FPGA and ad70676, the voltage collected by eight channels is printed out with serial port)

verilog实践 elc_clock 电子时钟设计(Verilog design practice elc_clock electronic clock)

基于VHDL的数字计时器，手动可控正计时和倒计时(含复位键和使能键)(VHDL-based digital timer and countdown timer being controlled manually (with the reset button and enable key))

FPGA实现增量式光栅尺正交脉冲解码，基于Verilog(FPGA realization of incremental grating ruler orthogonal pulse decoding, based on Verilog)