用Verilog HDL实现的uart通用串口通信程序，已经验证成功

能够实现16位的SDRAM的读写，没有仿真文件，只有SDRAM读写的源代码，用Verilog编写(can complete read or write sdram， only include Verilog code and no simulation files)

Based on the verilog such as frequency meter accuracy, except for measuring frequency can also measure pulse width of empty measure than 32 counts of data through the simulation SPI serial output to SCM processing and display

PD里面的4B5B编码，欢迎使用~~~~~~~~~~~~~~~~~(4B5B code in PD3.0 or USB3.0, welcome to use~~~~~~~~~~~~~~)

ldpc码的FPGA编译与仿真实现，欢迎分享，分享快乐。(LDPC code compilation and simulation。)

用FPGA verilog hdl模拟类I2C通信

它支持ahb接口它是一个内存模型，当传输完成时给出正常响应，当发现地址超出范围时给出错误响应

这是Uwe Meyer-Baese先生的代码，我有全部的代码，如果有人需要的话，可以联系我。haozix521@gmail.com

先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。(First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is detected with the preset test signal output " 1" , otherwise " 0" , and the detection display signal out.)

将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)

circuit design with VHDL e-book MIT Press....