简易制作呼吸灯小程序

这是一个VHDL项目，用于在VIRTEX-4 xc4vsx35 FPGA板中执行接收信号的14位ADC。

STT-MRAM磁性存储器全部verilog代码和仿真验证代码，包括行为模块，读写模块和控制模块，已经经过验证完全正确(STT-MRAM magnetic memory all the code and simulation code, including behavior module, reader module and the control module, has been proven entirely correct)

使用verilog HDL写的sdram(SDR)的控制器源代码，具有很好的可移植性，试验的例子已经通过QuartusII 9.0编译通过，可以运行在cycloneII上(Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII)

说明：  一个简单的千兆以太网UDP协议的实现,可以实现数据的收发和ARP，实现PC端与FPGA的以太网通信(A simple implementation of Gigabit Ethernet UDP protocol can realize data sending and receiving and ARP, and realize Ethernet communication between PC and FPGA.)

华为内部资料，包括verilog电路设计，硬件工程师手册，verilog约束，synplify使用指南等。内容较全面。(Huawei internal information, including verilog circuit design, hardware engineers manual, verilog constraints, synplify use guides. Content more comprehensive.)

基于FPGA的VGA彩条显示 可用PAXplusII仿真-FPGA-based VGA color display available PAXplusII Simulation of

说明：  verilog开发的经典教材，详细介绍了语法，常见历程，以及通用的程序段(verilog development of the classic materials, detailed information on syntax, common history, as well as the common program segment)

AL422B,FPGA写的控制时序。XIWANGDUIDAJIAYOUYONG(AL422B,timing of AL422b.)

用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.(algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company's paid Multiplier ip core.)

两位独立数码管100进制计数器，每1秒计数一次。从0到99，到99后又回到0.-Two independent 100-band digital tube counters, every time 1 seconds count. From 0 to 99, to 99 and then back to 0.