可实现找钱功能的自动售邮票机，可买两种邮票，一元的和五角的...

Frame Control field
Retry:
Set in case of retransmission frame
More fragments:
Set when frame is followed by other fragment
Power Management
bit set when station go Power Save mode (PS)
More Data:
When set means that AP have more buffered data for a station in Power Save mode

实现LDVS接口数据接收 含有协议结构以及处理(lvds Verilog 512 frame)

完整版的乘法器.相信对初学者有不小的提高-The full version of the multiplier. I believe there is not a small improvement for beginners

FPGA控制AD7321的模块，是本人亲自试验过的。有Verilog源码，和简单文档(Fpga control module of ad 7321, is I personally tested. Verilog source code, and simple documentation)

特大好消息，这是LED全彩控制卡的FPGA的源程序，做LED开发的，绝对有很好的价值(Big good news, this is full-color LED control card FPGA of the source, do LED development, the absolute value of good)

用FPGA实现DDS的原理图，结构清晰，采用总线方式与外部单片机通信-FPGA realization of DDS with the schematic diagram, structural clarity, the use of bus-way communication with the outside Singlechip

Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)

usb 和VGA接口FPGA程序，主控芯片为xilinx公司的SP3e系列的500E芯片，VHD语言编写，工程文件，可以直接用ISE打开

用Verilog语言编写的对m序列进行汉明码编译码的程序。具体实现为产生m序列后对其进行(7,4)汉明码编码并加错，然后将其纠错译码并输出，详细过程见仿真。(Written by Verilog m sequence of procedures for coding and decoding Hamming codes. Concrete realization of m sequence to produce its (7,4) hamming code and a mistake, and then error correction decoding and output, see the detailed process simulation.)

VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)