可实现找钱功能的自动售邮票机，可买两种邮票，一元的和五角的...

位同步例程源代码,FPGA应用领域，Verilog-Bit synchronization routines source code, FPGA applications, Verilog

MaxplusII编写的简易cpu，可实现简单加减法等操作(MaxplusII summary prepared by the cpu can realize simple addition and subtraction, etc)

UART功能,可以增加在NIOS2內,主要來做外部Flash的擦除及寫入,需搭配上位機傳輸字串來控制(UART function, can increase the NIOS2, the main external Flash to do the erase and write, to be a string with the host computer to control the transmission)

基于FPGA的误码测试仪 （已注释） --锁相环-M序列生成模块--数据接口模块- --模拟信道模块---本地M序列生成模块--同步模块--误码统计模块--显示模块-(FPGA-based BER tester)

四位数字乘法器，在quartus8.0下仿真时序图 -mult4

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现-Frequency-hopping communication QUARTUS7.0 expanded development environment in the VHDL source code and the achievement of the overall block diagram

verilog vga 图像处理(verilog vga)

一个数字电路设计：六层电梯自动运行的VHDL程序(a digital circuit:sixlift design)

stbc空时编码源码，非常好的程序。verilog程序-STBC Space-Time Coding Source, very good program. Verilog program

使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。(Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision)