对行为模型的全加器的VHDL代码

design through verilog hdl

使用VHDL编程的异步FIFO程序 经调试可运行-Using VHDL programming asynchronous FIFO procedure can be run by the debugger

异步串口通信口在FPGA实现，功能有（1）串行数据接收的同步控制；（2） 串行数据发送的同步控制-asynchronous serial communication port of the FPGA, function (1) serial data receiver synchronization control; (2) the transmission of serial data synchronization control

说明：  FFT 1024 point, in 10 state

说明：  libero soc工程，实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)

fpga串口的接收程序基于verilog语言拿走不用谢。(The receiving program of FPGA serial port is based on Verilog language.)

xlinx fpga实现fft功能，利用ip核，包含源程序及完整工程文件，直接就能使用(The fft function xlinx fpga ip-core contains the source code and complete the project file, and can be used directly)

protel中fpga封装库3，非常难找的-protel library in fpga package three, very difficult to find the

VHDL Project for beginners. Electronic dice game. Perfect for Spartan devices.

XAPP585 serdes_1_to_7 and serdes_7_to_1 data