对行为模型的全加器的VHDL代码

verilog 简易频率计的设置，包括整个工程(verilog simple frequency meter settings, including the entire project)

用vhdl实现双向移位寄存器 仿真环境MAXPLUS-II，QUARTUS--bidirectional use VHDL simulation environment shift register Segments-II, QUARTUS-

ldpc译码算法的matlab实现，码长960，码率1/2,完全模拟fpga硬件实现语言，量化处理。(ldpc decoding using matalb,code length 960,code rate 1/2)

说明：  FPGA 学习实例 动态时钟、面积、速度优化相关代码(Codes related to dynamic clock, area and speed optimization for learning examples of FPGA)

dc的应用规范，以及一些基础的操作指导，注意事项等(dc application specification, as well as some basic instructions, precautions, etc.)

用vhdl做的计算机组成原理课程设计的资料，实现加法运算，进行求和，仿真实例等资料！-Vhdl to do with the computer information on the composition of curriculum design principles to achieve the addition operation, a sum, simulation examples, etc.!

实现I2C协议下EEPROM存储的数据读写控制(Under I2C protocol to achieve read and write data stored in EEPROM control)

说明：  配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)

基于FPGA芯片，在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码！-Based on FPGA chip, the Nios II IDE software development environment written in NIos II soft-core uart source code!

基于sopc ep2c5开发板的时间标记服务例程-Sopc ep2c5 development board based on the time-stamping services routines