文档包括双线性插值算法和最近邻域算法的详细介绍，以及算法的相关计算。(Documentation includes bilinear interpolation algorithm and the nearest neighbor algorithm which is described in detail, as well as algorithms related calculations.)

用Verlog HDL编写的数字钟程序，包含时，分，秒，进位，解码，扫描显示等功能。-Written by Verlog HDL ，a digital clock program, including hours, minutes, seconds, into the place, decoding, scanning display.

viterbi译码器的IP核，可以直接编译使用-viterbi decoder IP core, the compiler can directly use

10进制计数器，VHDL描述的，实验必备-10 hexadecimal counters, VHDL description of the experiment must

ALTERA Cyclone1C20 Nios开发板，protel99格式-ALTERA Cyclone1C20 Nios，protel99

xc3s400芯片详细的英文资料，xc3s400的FPGA开发板使用者必看-chip xc3s400 detailed information in English, xc3s400 the FPGA development board users see

fpga verilog实现 S29GL256S 系列 并行 nor flash 的读写擦除操作功能。 verilog源代码。(Verilog S29GL256S to achieve FPGA series parallel flash nor read and write erase operation function. Verilog source code)

pcf8563，在quartusII下VERILOG编写的数字时钟程序，8位数码管显示(pcf8563, written in quartusII VERILOG digital clock program, eight digital display)

vhdl code for programming

Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!