用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware description language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.

用fpga实现VGA16色真彩的图片显示,且在AX301实验板上已经调试过(VGA16 achieve true color with fpga pictures show, and in the AX301 has been tuned breadboard)

用veriolg 语言编写的串口通讯程序，通过FPGA控制串口的通讯。(a veriog program completed on FPGA to contrlo a uart to communicaton with a computer )

matlab 程序 伪随机码的捕获,我传的都是这方面的资料！(failed to translate)

本文件是作为超大规模集成电路设计实验室课程（EC354）一部分进行的为期一学期的项目报告。我们的项目是一个4位8点FFT（快速傅立叶变换）核心的完全定制设计。实现的FFT类型是DIF（时间抽取）FFT。

Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。-Verilog HDL prepared by the five-frequency circuits. Clock using two phase logic role.

modelsim下的60进制计数器源码和测试激励文件(modelsim M counter 60 under the source file and test incentives)

本文为verilog的源代码-In this paper, the source code for Verilog

一些较为经典的VHDL代码,专注于信号分析与检测方面-Some of the more classic of the VHDL code, focusing on signal analysis and testing

图形图像H264插值算法，应用于图像视频处理(H264 graphic image interpolation algorithm is applied to image video processing)