access must be conf urr arr

基于单片机与CPLD的 等精度频率计，VHDL语言-Based on SCM and CPLD

fpga里实现 uart 经典 vhdl语言写的 ise工程文件-fpga implementation in vhdl language classic uart of ise project file

VHDL控制VGA 在显示器上显示图形，分辨率800X600，晶振50Mhz-VGA control with VHDL

Altera的CycloneIII Start Board,使用的PFGA是3C25，包括原理图和PCB，用Cadence Allegro打开-Altera

Cypress USB 的主从FPGA 控制实现代码(USB controller)

通过VERILOG编写的AD9516时钟芯片SPI配置代码(CONGIGURE THE ad9516)

说明：  通过MATLAB产生单脉冲信号的数据，存储下来作为verilog代码实现的DDS的数据源，用于验证DA数据的ddio的调试是否有问题。(The data of monopulse signal generated by MATLAB is stored as the data source of DDS implemented by Verilog code to verify whether the ddio debugging of DA data is problematic.)

本代码是用VERILOG语言描述的AMI码的解码的程序，经过调试是正确的。代码简单易懂。(This code is described in VERILOG language AMI code decoding process, after debugging is correct. Code is easy to understand.)

一些简单的VHDL实例，主要是介绍一些基本逻辑们及一些组合、时序电路的例子，供大家参考-Some simple examples of VHDL, mainly to introduce some basic logic and some combination of sequential circuit examples for your reference