在SOPC下制作自定义部件（PWM发生器）的源程序，包括硬件描述HDL文件和驱动程序文件...

讲解用FPGA及其他芯片组成视频处理的电路设计和PFGA的程序的实现-Explain the use of FPGA and other video processing chips of the circuit design and FPGA realization of the procedure

This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the

说明：  LIUSHUIDENG VHDLYUYAN XIADE SHUIDENG(LEDWATER I WRITER IT MYSILF.IT'S EASY ! YOU CAN WRITER IT,TOO)

以太网总线源代码，里面有详细的文档说明，已经过FPGA验证。-Ethernet bus source code, which has a detailed document that has been FPGA verification.

MMC卡的VHDL源代码实现，经过大批量生产验证-MMC card VHDL source code to achieve, through large-scale production test

LATTICE FPGA FIFO 程序例程，工程详细，全部源代码上传 (LATTICE FPGA FIFO routine, detailed engineering, all source code uploaded)

利用Verilog语言编写的，在vivado环境下带进位标志的全加器的工程文件与Testbench(Engineering files and Testbench of the full adder with the carry mark in vivado environment written by Verilog language)

说明：  系统介绍了数字开发系统平台FPGA设计中的部分技巧 对于FPGA开发研究人员具有一定的指导和帮助意义(Systematic introduction of digital development platform FPGA design techniques for FPGA development of some of the researchers have some sense of guidance and help)

NN CONTROLLER FOR UPQC

通信系统中数据的传输以帧为单位，在FPGA中帧头检测是通信系统中的一部分，该程序实现了FPGA中帧头的检测。(Transmission of data in a communication system in units of frames, the frame header is detected in the FPGA part of the communication system, the realization of the frame header is detected in the FPGA.)