分频程序

说明：  这是一款由晶振产生的脉冲控制的数字钟，可以从00:00:00到23:59:59之间进行计时。(this is a clolk controlled by continuious pulse.it can timing from 00:00:00 to 23:59:59.)

altera详细使用配置手册，有一定的参考价值，写的比较详细-altera in detail the use of manual configuration, has a certain reference value, a more detailed written

这是关于赢vhdl语言变得信号采集卡，很有实用性，大家可以来看看的。-This is about winning VHDL language has become signal acquisition card, is very practical, we can take a look at the.

四人抢答器，已通过编译，仿真，包括抢答识别、计分、计时、数字显示等功能。-Four Responder, has passed the compilation, simulation, including the answer in his identification, scoring, timing and digital display.

ASK,FSK,PSK,DPSK调制解调的详细仿真代码(ASK, FSK, PSK, DPSK modulation and demodulation detailed simulation code)

这是一个用VHDL语言实现的非常实用的表决器-This is a VHDL language with the very practical voting machine

DDS Verilog 代码。包含英文文档说明-DDS Verilog code. Containing the English documentation

基于FIR滤波器的LMS自适应算法的FPGA实现,verilog语言(FIR filter based on LMS adaptive algorithm on FPGA, VHDL language)

四人抢答器，包括主持人清楚按键，抢答后屏蔽其他三人的继续抢答，同时答题时间开始，答题时间三档可调。时间到后蜂鸣器发声，指示灯亮起。

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