EDA VHDL modules commonly used procedure, the time

基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41，基本实现了双向USB2.0 块传输（Bulk Transfer）通信，zynq的PS端接收USB数据并回传至主机。经测试，主机端Window10系统采用libUSBK编程时，采用64字节的块时，传输速率可达210Mbps。zynq开发工具为Vivado2015.4，程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)

用FPGA分频，做一个有时分秒的时钟，并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)

sram 读写小程序，用verilog编写的，请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master

Use verilog language design DIGITAL-PID source

页面置换算法中的三种算法相关程序代码 FIFO LUR OPT-yemianzhihuansuanfa

这是使用VHDL编写的交通灯程序,供大家交流学习-This is the use of VHDL prepared by the traffic lights procedures for the exchange of learning

卷积程序的Verilog程序，实现卷积功能(Convolution program Verilog program to achieve convolution function)

用VHDL编写的串口通讯程序，包括几个不同的程序例子，也可以用verilog进行改写。()

这是篇<基于FPGA 的OFDM 宽带数据通信同步系统设计与实现>, 觉得甚是有用，大家共同学学。(This is the article <FPGA-OFDM-based broadband data communication systems design and implementation of synchronous> that even be useful, we all learn together.)

网上分享的一段100例子，适合FPGA学习的初学者。内部还有一些经典实用技巧。