这是使用VHDL编写的交通灯程序,供大家交流学习

这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)

Viterberi 解码器使用 vhdl 编程实现将被用于制作增强功能

VHDL参考例程--日如DAC0832接口电路程序-VHDL reference routines- on procedures such as the DAC0832 Interface Circuit

实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。-experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting.

verilog语言实现一个CPU，汇编程序实现汉明编码功能，输入11位代码，输出15位编码结果。(Verilog language to achieve a CPU, assembler to achieve Hamming coding function, enter 11 bit code, output 15 bit encoding results.)

vhdl项目设置： flv的 -VHDL Project Settings: flv

de2_clock on altera de2 board

本程序主要是实现xinlinx fpga与dsp之间的双工通信(This program is to achieve duplex communication between xilinx fpga and dsp)

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the

verilog HDL经典的入门书籍，内容很详细，讲了许多实例，适合硬件描述语言初学者。(verilog HDL classic introductory book, the content is very detailed, spoke many instances, suitable hardware description language for beginners.)