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Using VHDL programming asynchronous FIFO procedure can be run by the debugger
使用VHDL编程的异步FIFO程序 经调试可运行-Using VHDL programming asynchronous FIFO procedure can be run by the debugger
- 2022-03-23 14:37:37下载
- 积分:1
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integrator
this code for integrator for 8 bit signal
- 2010-01-07 16:06:04下载
- 积分:1
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PrinciplesofVerifiableRTLDesignpart2
非常好的verilog书
国际牛人写的
适合各个阶段学习的人(Very good Verilog books were written in the international cattle suitable for the various stages of learning)
- 2007-09-28 11:26:38下载
- 积分:1
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FPGA设计中的一些经典例子对学习FPGA的人会有帮助...
FPGA设计中的一些经典例子对学习FPGA的人会有帮助-FPGA design of some of the classic examples of people learning FPGA would be helpful
- 2022-05-23 13:59:58下载
- 积分:1
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ADC_Data_Recv_Module
接收机测试输入信号,
生成正余弦波,采样率、频率、幅度、相位可调节
并将生成的数据进行输出
压缩包包括Verilog代码、testbench代码、word文档
matlab仿真代码(The receiver tests the input signal,
Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted
And output the generated data
The compressed package includes the Verilog code, the testbench code
Matlab simulation code)
- 2017-12-08 17:56:02下载
- 积分:1
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can_init
说明: 通过SPI接口实现FPGA和MCP2515独立CAN芯片通信,功能使用modelsim仿真,实现了配置、接收、发送功能。(The communication between FPGA and MCP2515 independent can chip is realized by SPI interface. The function is simulated by Modelsim, and the function of configuration, receiving and sending is realized.)
- 2020-12-30 09:28:59下载
- 积分:1
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LM
说明: 用于生成adams或recurdyn所需的路面不平度,用于悬架或其他的仿真(Adams or recurdyn used to generate the required road roughness for suspension or other simulation)
- 2013-10-15 17:38:48下载
- 积分:1
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fenpin
这是一个二进制的最简单分频器,是一个简短的fpga代码,用verilog书写(This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog)
- 2013-11-17 15:01:30下载
- 积分:1
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vhdl,十进制加减计数器,输出计数序列信号
vhdl,十进制加减计数器,输出计数序列信号-vhdl, decimal addition and subtraction counter, the output count sequence signal
- 2022-02-07 17:03:29下载
- 积分:1
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在EFF的代码地址异步FIFO的灰色代码详细设计…
详细设计了异步fifo格雷码中地址码的生效和Man标志的出现
- 2022-02-07 05:32:22下载
- 积分:1