verilog ADPLL file with testbench

由于在网上很难下载到EDA技术－窦衡的PPT，所以本人经过学习后做成word，供大家下载。只针对VHDL语言部分和所有的程序。-Because the Internet is difficult to download to EDA technology- Douheng of the PPT, so I made after learning after the word, for all to download. Only for part of the VHDL language and all the procedures.

SRAM 读写实验，SRAM存储器的读写操作，Verilog源码有助于提高代码coding能力。使用例程。(SRAM write and read)

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利用c控制adc，主要是控制字写入，状态控制。-C control the use of adc, is mainly controlled write, the state of control.

Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)

OFDM系统中的相位跟踪模块（Phase_Tracking）的FPGA实现-Phase_Tracking in OFDM sysytems

高速FIFO，verilog设计。速度高达130Mhz-High-speed FIFO, verilog design. Speed up to 130MHz

任意奇数分频，只要修改N即可实现 可验证-Arbitrary odd-numbered sub-frequency, as long as the modified N can realize verifiable

一个求反余弦的cordic算法，整个工程。包括仿真。可以直接打开。(An inverse cosine of the cordic seeking algorithms, the whole project. Including the simulation. Can be directly opened.)

利用FPGA实现硬件的VHLD语言的Manchester code。(Hardware implementation using FPGA VHLD language Manchester code.)