verilog ADPLL file with testbench

曼彻斯特编解码 Xilinx提供的VHDL的源代码-Manchester codec Xilinx provide VHDL source code

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现对4x4键盘的输入控制，并显示在一个8段式数码管上。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 the development board to realize 4x4 keyboard input control, and displayed in an eight-stage digital pipe.

详细讲解时序约束培训教材，有利于更好对时序约束的理解(Timing constraints elaborate training materials, facilitate better understanding of the timing constraints)

68013与FPGA的通信，包含了固件程序与verilog程序(68013 and FPGA communication, including firmware and verilog program)

fpga串口的发送程序基于verilog语言拿走不用谢。(The sending program of FPGA serial port is based on Verilog language.)

用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写(verilog ise divider)

简单介绍了直接数字频率合成技术(DD S)，利用DDS设计任意 波形发生器，其能够产生矩形波、正弦波、三角波、锯齿波等多种波形 -A brief introduction of direct digital frequency synthesis (DD S), the use of DDS design of arbitrary waveform generator, which can produce rectangular wave, sine wave, triangle wave, sawtooth waveform etc.

实现了QPSK的调制，使用了ise自带的dds的IP核(QPSK is modulated and the IP core of DDS is used in ise.)

1024点fft verilog hdl-1024-point fft verilog hdl

乘法器的vhdl语言描述.本人调试已经通过-Multiplier described in VHDL language. I have been through the debugging