Several Example FPGA design contest

altera官方的各种有用的参考资料，都是自己收集的，遇到问题可以很方便的查看(altera official variety of useful references, are their own collection, problems can easily view)

四位动态刷新数码管显示，ＶＥＲＩＬＯＧ代码，含详细的中文注释．-Four dynamic refresh digital tube display, VERILOG code, with detailed notes in Chinese.

对pci9054芯片的配置进行了设置，并对PCI9054的各状态机进行了设置，程序经过了测试(Pci9054 chip on the configuration of the set, and each state machine PCI9054 been set, the program have been tested)

10对于进入密码锁的按键，假设复位后七个灯显示0，使用sw1、sw2两个键输入，只要按sw1键，并使七个灯显示每秒速度加1的值，但释放sw1键后停止。

designing of 16 bit adder using 4 bit adder using verilog code

papers based on distributed arithmetic.

基于DE2开发板的VGA显示模块，仅供大家参考-DE2 development board based on the VGA display module, for your reference

FPGA设计中的时序分析及异步设计注意事项 (FPGA design timing analysis and design considerations for asynchronous)

io 组件，用vhdl实现io端口的控制，包括输入输出，握手信号，-io port VHDL code

crc5 bolck in usb contreoller