Several Example FPGA design contest

内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging

这是Xilinx ISE 14.X以及vivado、vivado_hls的license，亲测可用(Xilinx ISE 14.x vivado, vivado_hls license, pro-test available)

本代码仿真了WCDMA小区搜索。cell_search_cpich scramble wcdmasource(This code emulation WCDMA cell search. cell_search_cpich scramble wcdmasource)

基于FPGA，利用VHDL语言对小车循迹进行设计。(Car tracking)

vga显示代码,里面有ise工程文件,是直接调过去的,大家下载下来吧-vga display code, which has ise project file is transferred directly past, everyone download it

说明：  本书纸版由机械工业出版社于2014年出版，张强编著，电子版由华章分社（北京华章图文信息有限公司）全球范围内制作与发行(The book was published in paperback by China machine press in 2014, and edited by zhang qiang. The electronic version was produced and distributed worldwide by huazhang branch (Beijing huazhang graphic information co., LTD.))

数字电子钟用自拍图像代替了内置图像的石英制作

设计遥控器接收解码电路。该电路接收编码后的串行数据，解码输出数据。电路接收 到的串行数据的格式为： 4 位同步码“ 1010”， 4 位数据（高位在前）， 1 位奇校验码（对前 8 位数据校验）(Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial data received by the circuit is: 4 bit synchronous code "1010", 4 bit data (high in the front), 1 bit parity check code (check for the first 8 bits of data))

8b10b编解码，用于光通信和千兆以太网，verilog编写，已验证(8b10b codec for optical communications and Gigabit Ethernet, verilog prepared Verified)

16位有符号和无符号乘法器FPGA源代码(16-bit signed and unsigned multiplier FPGA source code)