Several Example FPGA design contest

载波同步的verilog代码，是新手学习同步的最佳选择，值得推荐。(Verilog code carrier synchronization, synchronization is the best choice for novices to learn, it is worth recommending.)

lvds transmitter megafunction (lvds transmitter megafunction)

ofdm_cp_insertion add/remove CP

Verilog HDL 读取EEPROM项目的详细构建(Verilog HDL EEPROM read the detailed construction)

基于FPGA的技术溢出研究程序，只是一个测试程序，大家可以下着用一下。-FPGA-based research process of technology spillovers is only a test procedure, we can next look forward to using.

数字逻辑课程设计，用vhdl实现红外线传输系统的课程设计，下载验证通过-Digital logic course design, using vhdl infrared transmission system to achieve curriculum design, download verified by

this is a verilog code for root raised cosine filter

正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim

无线通信FPGA设计Matlab Verilog代码(Wireless FPGA design Matlab Verilog code)

本文为verilog的源代码-In this paper, the source code for Verilog