8 位加法器 verilog

单周期CPU自己课程大作业做的，亲测好用，verilog语言，适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)

说明：  将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)

数字下变频（DDC）在如今基于软件无线电的架构中对系统的整体性能决定性的影响，代码为基于Matlab的4通道DDC程序，程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值(Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code for the 4-channel DDC Matlab-based program, the program can be adjusted according to filter parameters such as the use of performance assessment FPGA DDC DDC has achieved great reference value)

自己用verilog编写的crc16-ccitt码的产生，是并行的。(Crc16-ccitt code written in verilog generate parallel.)

AES加密算法verilog源码 This project is the hardware implementation of the  Advanced Encryption Standard with a key size of 128 bits. The implementation adheres to the FIPS-197 document which explains the same.The core can do both encryption as well as decryption.The documents aes_arch.doc and aes_tb_readme.txt give further details of the rtl implementation and test bench respectively. This code was written originally with 128 bit ports for both input and key but later converted to 64 bits each to save on i/o pins. It can be reverted back easily if one just changes the port widths and dispenses with the load signal in the top module and making approriate changes in process where load is used.Synthesis results have been included for Xilinx Spartan-3 device.The directory structure of the project is as under- AES128

32-bit Wishbone Interface • DMA • Buffer Descriptor • Compliant with SD Host Controller Spec version 2.0 • Support SD 4-bit mode • Interrupt-on-completion of Data and Command transmission • Write/Read FIFO with variable size • Internal implementation of CRC16 for data lines and CRC7 for command line Wishbine 总线使用。完整的SD卡控制器，支持文件系统，高速传输。

fir低通滤波器 用于dspbuilder pll：25nss data 400khz sin 10.8khz 已通过测试。 (fir low pass filter for dspbuilder pll: 25nss data 400khz sin 10.8khz has been tested.)

基于Verilog HDL的SDRAM控制器。 实验条件： 工具：Quartus II 6.0 ,SignalTap II FPGA：Altera Cyclone EP1C12Q240C8N SDRAM：HY57V283220T-6(SDRAM controller based on Verilog HDL. Experimental conditions: Tools: Quartus II 6.0, SignalTap II FPGA: Altera Cyclone EP1C12Q240C8N SDRAM: HY57V283220T-6)

说明：  用uvm验证方法学验证异步fifo，文件包括异步FIFOrtl代码和uvm组件(Verification of asynchronous FIFO with UVM)

说明：  简单的一个Verilog小程序，适合刚接触的人群(A simple Verilog small program, suitable for people just contact)