cordic 算法

基于 hdl语言的re232通信实验的设计，程序简单明了，一学就会(rs232 communication)

贪吃蛇程序，用verilog实现，可以运行只要修改一下相应的FPGA芯片类型和VGA接口相应的引脚(Snake program, using Verilog to achieve, you can run as long as the appropriate to modify the corresponding FPGA chip type and VGA interface to the corresponding pin)

高电平置数，高电平清零的同步D触发器

HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)

all funtions for a scale meter for maps in a 8051 microcontroler with an alphanumeric lcd display

verilog 有符号数 乘法器模块(verilog signed multiplyer)

我用FPGA来实现，这是一个出租车计价器，用来计算里程，我已在Quartus 2实现。(I used the FPGA to achieve, this is a taxi meter, calculate the mileage, I have been in quartus 2 to achieve.)

说明：  quartus vitual jtag代码使用接口，通过该接口模板方便使用者通过jtag在线读取FPGA的数据。(The quartus virtual JTAG code uses an interface, through which users can read FPGA data online.)

艾米电子的verilog HDL描述的DS18B20的程序(Amy verilog HDL description of the procedures DS18B20)

摘要可逆逻辑本身是一个突出的、具有重要意义的技术，在这一技术中起着重要的作用