full adder设计代码，verilog 语言描述，通过modelsim 仿真，quartus综合...

他延误用户inrandom经历过或基于竞争的MAC方案是无界;用户可能需要等待论坛很长一段时间，直到他/她发送一些数据的机会。在otherhand，通过根据一定的deterministicpattern，这被称为由梅西和马特仕协议序列调度所述数据分组，延迟的hardguarantee可以完成。

说明：  激光测速研究，主要介绍多普勒激光测速知识(Laser velocimetry study introduces laser-Doppler velocimetry knowledge)

DEMO中完成WIAGAND26/32的（EMP7128实现）协议程序源代码-DEMO completed WIAGAND26/32 (EMP achieved) agreement procedure source code

2008-2009年优秀硕士论文之：基于FPGA的高性能32位浮点FFT IP核的开发(Outstanding Master' s thesis 2008-2009: FPGA-based high-performance 32-bit floating-point FFT IP core development)

verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏(verilog description of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted, within the simulation images png screenshots)

矩阵键盘控制的FPGA，verilog语言实现，包括rtl，ucf,以及testbench的详尽代码(Exhaustive code matrix keyboard control FPGA, Verilog language, including the rtl, ucf, and testbench)

this code for integrator for 8 bit signal

Xilinx fpga 设计培训中文教程,比较好的学习FPGA入门的教程(Xilinx fpga design training for Chinese curricula, better start learning FPGA Tutorial)

使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.

Generating a wider ALU from two small ones