full adder设计代码，verilog 语言描述，通过modelsim 仿真，quartus综合...

这是基数 4 修改 Booth 型乘法器为 8 位。它可以用于任何大小的操作数的乘法......

利用Verilog编写一个交通灯控制电路，能控制两条路上红、黄、绿灯的变化，并且显示等待时间(Using Verilog HDL to design a traffic light control circuit. It can control the change of red, yellow and green lights on two roads, and display the remaining waiting time.)

本源码为Nios II的开发示例,主要演示Nios II的SPI总线设计。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II design of the SPI bus. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

用verilog写的很好的cpu core-using Verilog write a good cpu core

cic设计 verilog verilog(cic verilog design verilog)

矩阵求逆模块硬件实现,用verilog语言，基于ISE开发环境(implement of inverse matrix)

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-(use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-)

It is a example about LCD by VHDL code

vhdl写的ds18b20程序，相互交流-vhdl written ds18b20 procedures, mutual exchange

Commponent for drivering EEPROM memory AT25320 from Avalon bus.