full adder设计代码，verilog 语言描述，通过modelsim 仿真，quartus综合...

广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)

ds1302时钟驱动程序，已在quartus上验证可以是直接使用(DS1302 clock driver, which has been verified on quartus, can be used directly)

实现了UART的底层协议，加入了控制器，其波特率可以根据使用进行调整；发送模块、接收模块相互独立，互不影响。(Realization of the underlying protocol UART, joined the controller baud rate can be adjusted according to use transmission module, receiver module are independent of each other.)

n_bit_paralleLoadShiftRegJK

主要通过频率分配 实现不同时间的变化 达到呼吸一闪一闪的效果

电子设计自动化中关于交通信号的转换的实现程序，基于VHDL语言实现的-Electronic design automation in the conversion of traffic signals on the realization of the procedure, based on the realization of VHDL language

说明：  基于Verilog语言编写的LCD1602显示的日历程序，类似时钟功能值得参考。(LCD1602 shows calendar program based on Verilog language, similar clock function is worth reference.)

本源码为Nios II的开发示例,主要演示Nios II的SPI总线设计。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II design of the SPI bus. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

说明：  OFDM信号的发送与接收 ，需要自取。时域图，模糊图，削峰。(Sending and receiving of OFDM signal)

用VERILOG实现一个被除数为8位、除数为4位的高效除法器(With VERILOG implement a dividend for the 8-bit, 4-bit effective divisor divider)