full adder设计代码，verilog 语言描述，通过modelsim 仿真，quartus综合...

基于ALtera公司的若干款FPGA的调试经验，对初学者有重要价值-ALtera a number of sections based on the company" s FPGA debugging experience, great value for beginners

本文件是用CPLD（EPM7064）驱动线阵CCD（ILX509），其中包括原理图和程序-This document is a CPLD (EPM7064) driver line array CCD (ILX509), including schematics and procedures

verilog 教程 PPT版本 语法 结构 设计技巧等(Verilog tutorial PPT version)

一个完整的信号测试程序,对信号的各项指标进行完整的测试,并分析-A complete signal test procedures, the various indicators of signal integrity testing, and analysis of

此文件给出了一个多功能交通灯的VHDL代码实现，可作为电赛的准备材料-This paper gives a multi-functional traffic lights to achieve the VHDL code can be used as electric materials Cup preparations

Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.

通过vga通讯控制显示器显示七彩条文，通过quartus编译的程序，可用-Communication and Control through the vga display colorful provisions quartus compiled through the procedures that can be used

VHDL ip core的设计，软核的设计方法-VHDL core of the design, soft-core design

buffer for in/out data.

说明：  verilog标准语法，还有很多的样例参考，学习的好资料。(Verilog standard grammar, there are many examples for reference, good learning materials.)