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spi_interface
说明: spi通用串行总线,4线控制,可读写操作(SPI universal serial bus, 4-wire control, readable and writable operation)
- 2019-04-29 12:37:55下载
- 积分:1
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三种方法编写多路选择器的VHDL源代码
分别使用if else ,select ,when 语句...
三种方法编写多路选择器的VHDL源代码
分别使用if else ,select ,when 语句-three methods to prepare multiple choice of VHDL source code were used if else, select, when words
- 2023-02-04 23:35:03下载
- 积分:1
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VHDL实现led灯的动态扫描,主要对CLK进行分频
VHDL实现led灯的动态扫描,主要对CLK进行分频-VHDL realization led lamp dynamic scan, the main points of the CLK to the frequency
- 2023-03-21 08:35:04下载
- 积分:1
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VGA显示驱动程序编写的Verilog HDL
用Verilog HDL编写的VGA显示驱动程序-Verilog HDL prepared with VGA display driver
- 2022-03-19 09:42:23下载
- 积分:1
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半加器
它包含与试验台硬件描述语言(VHDL)一半加法器试验台意味着项目制造商宣布他要什么时候能给一个术语 请点击左侧文件开始预览 !预览只提供20%的代码片段,完整代码需下载后查看 加载中 侵权举报
- 2023-05-06 00:50:07下载
- 积分:1
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此示例是8051核加频率计的联合设计,带有8051IP核资料
此示例是8051核加频率计的联合设计,带有8051IP核资料-This example is the 8051 nuclear increase the frequency of joint design, with the nuclear information 8051IP
- 2022-06-14 22:57:42下载
- 积分:1
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RISC
说明: RISC全部源码,包含仿真文件,使用makefile脚本编写,能通过vcs编译(RISC all source code, including simulation files, using makefile script, can be compiled through VCS)
- 2020-04-14 22:10:52下载
- 积分:1
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dingshi
定时器加数码管显示源码,以及test bench测试模块源码,经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)
- 2013-07-27 10:34:41下载
- 积分:1
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AD
说明: 基于fpga的ad采样程序 可控制ad9226对信号进行采样(Ad9226 signal sampling can be controlled by ad9226 sampling program based on FPGA)
- 2019-07-30 14:00:57下载
- 积分:1
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VHDL实现交通灯
VHDL实现交通灯-VHDL traffic lights
- 2022-04-07 20:09:13下载
- 积分:1