3 位到 4 位解码器

LCD 驱动的IPCORE，可用于alteraFPGA(LCD driver IPCORE, can be used to alteraFPGA)

Programmable IIR Filter written in Verilog and its respective modules.

Frame Control field
Retry:
Set in case of retransmission frame
More fragments:
Set when frame is followed by other fragment
Power Management
bit set when station go Power Save mode (PS)
More Data:
When set means that AP have more buffered data for a station in Power Save mode

串口接收模块 Verilog serial port receiver module，包含bps产生模块，电平检测模块和控制模块

CORDIC(Coordinate Rotation Digital Computer)算法即坐标旋转数字计算方法。 CORDIC算法,能够通过平移和累加快速实现基础的数学函数,包括三角函数,开方,指数,对数,平方根等函数。(CORDIC (Coordinate Rotation Digital Computer) algorithm for the coordinate rotation digital calculation. CORDIC algorithm can be achieved through the rapid translation and accumulation based on mathematical functions, including trigonometric, square root, exponential, logarithmic, square root and other functions.)

hdmi 视频编解码输入输出模块，verilog实现(hdmi encoder and decoder in verilog.)

说明：  使用XILINX公司提供的板子里面的FFT的IP核，很好用(XILINX board provided the use inside the FFT of the IP core, useful)

主要是主机对寄存器进行配置传输数据

设计一个十进制计数器，具有显示位置随计数时钟在八个数码管中左右滚动的功能。(Design of a decimal counter, a display position with the count clock in at around eight digital scrolling function.)

verilog实现VGA显示。有源代码，大家可以下载学习。