rs232串口协议

LVDS De-serialization

4x4鍵盤使用語法為VHDL，基於cyclone(4 x 4 keyboard using VHDL)

用verilog语言实现的除法器，实现方式为移位减

usb3.0 物理层仿真，verilog编程(Start the physical simulation)

1024点fft verilog hdl(1024-point fft verilog hdl)

实践的打井不工作，只是尚未尝试测试出多一点，不是最后的版本 ！

基于COMTEX-M3的IEEE1588,irigB对时的源程序，包括GPS对时程序，并将对时的结果写入FPGA中(Based COMTEX-M3 of IEEE1588, irigB on time source, including GPS for the program, and writes the results when the FPGA)

本文介绍一种波导双模双带滤波器的设计方法。(This paper presents a new class of dual-mode dualband filters in which each polarization is dedicated to a selected band. The equivalent circuit is a parallel combination of two inline networks that represent each polarization. A transmission zero is generated between the two bands by properly adjusting the relative orientations of the input and output coupling apertures.)

用流水线的方法实现16位乘法器，运算速度快，消耗时钟资源少(Pipeline method to realize 16-bit multiplier, which is fast in operation and consumes less clock resources)

电路在语言中建模与入席，保存和显示数据与一个重置按钮 7 分割。