SDRAM的控制程序，特权同学的源代码

目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下(The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.)

在FPGA内部实现数据大小排序是一件非常困难的事情，本例中以流水线方式实现16个数据的排序！

此代码是实现DPA。

Bringing SMW2:YI Back To LIFE Through Rom!

TCM编码的调制端，采用8PSK，2/3码率的卷积码的matlab程序(TCM coded modulation client, using 8PSK, 2/3 code rate of convolutional codes of matlab program)

German REAL LPT! USB2LPT

ALTERA on chip fifo. this document is from altera. good resouce

说明：  基于FPGA的1553b接口设计详细设计论文(1553B design based on FPGA)

timblogiw.c timberdale FPGA LogiWin Video In driver.

Xilinx 公司Spartan-6系列FPGA实现LVDS，带Modelsim仿真文件，已综合。(Xilinx Spartan-6 Series FPGA implements LVDS with Modelsim simulation file, which has been synthesized.)