16points FFT Verilog

说明：  通过按键输入学号，并循环显示： 电路功能描述：通过Ego1上的按键输入自己的学号（8位10进制数），并存储在32位的寄存器中；8位10进制数输入完成后，实现滚动显示效果。(Enter the student number by pressing the key, and display it in a cycle: Circuit function description: input one's own student number (8-digit decimal number) through the key on ego1, and store it in 32-bit register; after the completion of 8-digit decimal number input, the scrolling display effect is realized.)

它是一种算法，它是用来在超大规模集成电路的乘法2

A VANET research program

ldpc的算法介绍及其fpga上硬件实现(Introduction of LDPC algorithm and Its FPGA implementation)

基于fpga的led点阵控制系统软件程序设计(Led dot matrix control system based on fpga software program design)

DESCRIPTION OF FULL ADDER

sdram_cmd.v是控制sdram的命令集合。网上资料，是控制sdram的命令集合。网上资料。控制sdram的命令集合。网上资料控制sdram的命令集合。网上资料。

ads1255 spi verilog驱动,已测试过，可以使用。

说明：  配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)

说明：  关于地铁售票的一些功能 基于自动买票的VHDL设计程序 比较经典(Subway ticket on some of the features of the VHDL-based auto-buying classic design procedure)