Verilog_HDL源码， Verilog_HDL源码

EP2C35A实验箱基于NIOSII的串行AD_DA编程(EP2C35A experimental box based NIOSII the serial AD_DA programming)

fsk调制与解调，此程序经过验证，可以运用，通讯方面的同学可以用-FSK modulation and demodulation, this procedure has been verified and can use communications students can use

基于单片机和FPGA实现DPSK调制解调的功能和分类比较。(MCU and FPGA implementation based on DPSK modulation and demodulation functions and classification comparison.)

FPGA的卷积编码小程序，VHDL描述，参数为2，1，7.(2,1,7 cov with VHDL.)

verilog实现的1024位的大数模逆算法，引入RAM作为数据通道-verilog to achieve the 1024 Modular inverse algorithms, the introduction of RAM as a data channel

ＵＣ1698Ｕ驱动160*160ＬＣＤ中文应用及例程(UC1698U driver 160* 160LCD Chinese applications and routines)

CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.-CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.

FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)

先用Matlab理论仿真，再用Verilog语言在ISE环境下编写程序，可通过手机发送指令来控制上下变频器的参数。(Firstly, we use the theory of MATLAB to simulate, and then use Verilog language to write programs in ISE environment. The parameters of up-down converter can be controlled by sending instructions from mobile phone.)

file_read vhdl code provide by my teacher for reading file into FSM-file_read vhdl code