Verilog_HDL源码， Verilog_HDL源码

Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。-Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used.

使用STM32官方提供的DSP库进行FFT，虽然在使用上有些不灵活（因为它是基4的FFT，所以FFT的点数必须是4^n），但其执行效率确实非常高效，看图1所示的FFT运算效率测试数据便可见一斑。该数据来自STM32 DSP库使用文档(. Using the official DSP library provided by STM32 for FFT is not flexible in use (because it is the FFT of base 4, so the number of FFT points must be 4 ^ n), but its execution efficiency is really very efficient, as can be seen from the test data of FFT operation efficiency shown in Figure 1. This data comes from STM32 DSP library usage document)

定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)

verilog code for apb to ahb convert

vhdl状态机设计,文件简单详细易懂，可以使用在交通灯，文件配置等系统上。(vhdl state machine design, simple, detailed and easy to understand, you can use the traffic light system file configuration file.)

一个关于降低现代通信系统中高峰均比信号的matlab算法，对于研究数字预失真基于FPGA实现的有一定作用！(A modern communication system on the lower than the peak signal matlab algorithm for FPGA-based study of digital pre-distortion to achieve a certain effect! )

VHDL 洗衣机程序，可实现定时、报警、洗衣，脱水等等功能。底层为VHDL文件，顶层为电路图连接

利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance. )

高效的同步有限状态机的设计，本代码详细的说明了如何设计高效和规范的fsm设计-Efficient Synthesizable Finite State Machine Design using NC-Verilog

进阶实验之SRAM测试，由verilog编写，可直接对sram进行存写(Advanced SRAM test experiments, written by the verilog, can be stored directly on the sram write)