Verilog_HDL源码， Verilog_HDL源码

展位的乘法算法 is a 乘法算法两者相乘得两个签名二进制 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

并行读写14路串口数据，数据被写入FIFO，在收到读写信号后，SPI发送数据出去(Parallel read and write 14 serial port data, SPI send data)

闪耀光栅 有带阻滤波器作用的闪耀光纤光栅，反射角度可以控制(Blazed grating)

基于CPLD芯片EPM570的verilog hdl串口程序(the UART verilog hdl code based on CPLD chip-- EPM570)

this program get 20 point from user and draw functions.

VHDL Code For Full Adder By Data Flow Modelling

一种RISC结构8位微控制器的设计与实现-The structure of a RISC micro-controller" s 8 Design and Implementation

用于Altera公司DE2开发板的TV demonstration-Altera Corporation for DE2 development board of the TV demonstration

实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)

altera官方的各种有用的参考资料，都是自己收集的，遇到问题可以很方便的查看(altera official variety of useful references, are their own collection, problems can easily view)