Verilog_HDL源码， Verilog_HDL源码

this example finds the gapes that are existed in a word

说明：  电网协议信道解交织器设计FPGA实现，适用于PB16的宽带电力线载波通信(Grid protocol channel deinterleaver design FPGA implementation, suitable for PB16 broadband power line carrier communication)

基于fpga的出租车计费系统，采用自顶向下的设计方法-FPGA-based billing system of a taxi, using top-down design methodology

高效的同步有限状态机的设计，本代码详细的说明了如何设计高效和规范的fsm设计-Efficient Synthesizable Finite State Machine Design using NC-Verilog

this is a vhdl program...

开发板原理图 自己可以设计开发板为什么一定要买呢(Development board schematic can design their own development board why they must buy it)

数字时钟的VHDL语言描述，具有高精度，控制性能良好-Digital Clock description of the VHDL language, with high precision and good control performance

说明：  SDRAM的驱动程序，主要是对SDRAM各类状态进行驱动，有刷新模块、读、写模块等。(The driver of SDRAM mainly drives various states of SDRAM, including refresh module, read and write module.)

用VERILOG编写的VGA字符显示，可以在电脑屏幕上显示字符,已通过测试(Prepared with the VERILOG VGA character display, can display characters on a computer screen, has been tested)

hdlc协议的封装与解析，fsc校验，完整的例程代码(Decode and Encode an HDLC packet ，using FCS16 calculation)