VHDL语言实现PWM信号，非常方便的使用

first in first out 的说明文档以及时序图 对学习FIFO很有帮助(first in first out the documentation and the timing diagram helpful in learning FIFO)

《Verilog HDL 程序设计教程》6-"Verilog HDL Design Guide" 6

基于FPGA的多波形发生器 基于FPGA的多波形发生器-FPGA-based multi-waveform generator based on multi-FPGA Waveform Generator

Quartus环境下的7段扫描显示电路的源程序(Quartus environment of the seven scanning display circuit of the source)

几大代工厂的flash verilog源代码(flash verilog code)

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License

本文件介绍的是用VerilogHDL语言设计分频器和32位计数器.(This paper presents the design using Verilog HDL language Frequency Divider and 32 counters.)

verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.

VHDL设计实体的基本结构 VHDL的语言要素 用VHDL实现电路设计的方法 VHDL设计流程-VHDL design entities, the basic structure of the language element of VHDL using VHDL circuit design approach to achieve VHDL design flow

RAM读写控制器，用verilog实现的简单易懂的RAMROMsram控制核-Controller RAM read and write, using verilog implementation of easy-to-understand control of nuclear RAMROMsram