3。这个核心的分配必须是免费的。充电

fifo异步串口收发程序 FPGA程序(fifo asynchronous serial transceiver)

crc循环冗余校验码，用于对传输信号进行编码校验，是信息更可靠-crc cyclic redundancy check code used to transmit coded signals to verify, the information is more reliable

spartan605评估板测试代码。xilinx官方资料(spartan605 uation board test code)

该工程用verilog编写，已通过串口调试助手调试通过，接收模块采采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。 (The project is written in verilog debugging through serial debugging assistant, adopted 8 times the baud rate sampling data receiver module, better filtering done on the PC spontaneous self-closing function.)

与单片机相比，用CPLD/FPGA器件更适合于直接对高速AD采样控制。本实验接口器件为ADC0809，根据ADC0809的工作时序使用CPLD产生该控制信号，CPLD启动AD转换后，得到的数据送至单片机并在PC机及数码管上显示AD转换结果。(Compared with the microcontroller, CPLD/FPGA devices more suitable for direct sampling control of high-speed AD. The interface of the experimental device for the ADC0809 ADC0809 Timing CPLD is used to generate the control signal, the CPLD to start the AD conversion, the data sent to the microcontroller and the AD conversion result on the PC and digital tube display)

超前进位加法器得VHDL实现小点资料代码(CLA was a small point of information VHDL code)

基于fpga的液晶驱动开发过程相关资料，用于借鉴和学习-Fpga-based LCD driver development process relevant information, for reference and learning

红色飓风II开发板USB2FPGA USB驱动程序，由verilog编写，包括源码和FIFO测试程序(Red Hurricane II development board USB2FPGA USB driver from verilog preparation, including source code and test procedures FIFO)

实现音频的I2S通信，音频柱的显示，及其噪声的处理等功能(Realization of audio I2S communications, audio column display, and its noise processing, and other functions)

this a spartan 3E base project file. this is the project of game in which vga is interfaced to FPGA. this file is main file in which vga timing is maintained.-this is a spartan 3E base project file. this is the project of game in which vga is interfaced to FPGA. this file is main file in which vga timing is maintained.