移位相加硬件乘法器,基于FPGA的VHDL语言编写的,含有全部文件

多功能数字钟，在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)

32bits FIFO with synchronizer. pass the synthesis using Synopsys tools-bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools

xilinx accel dsp实例项目工程-xilinx accel dsp project

crc5 bolck in usb contreoller

本代码是实现了lwip协议栈,可以移植到其他类型的嵌如式操作系统上-This code is to achieve a lwIP protocol stack can be ported to other types of embedded operating systems such as the type

实现LDVS接口数据接收 含有协议结构以及处理(lvds Verilog 512 frame)

verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)

Quartus2环境下基于VHDL状态机的交通灯程序(VHDL state machine traffic lights based on Quartus2 environment)

高速FIFO，verilog设计。速度高达130Mhz(High-speed FIFO, verilog design. Speed up to 130MHz)

DS18B20温度传感器，用verilog语言实现(DS18B20 temperature sensor, with the verilog language)