VerilogHDL.自动增益控制模块中产生控制电压的部分

用Verilog HDL语言进行HDB3编码，并通过Quartus Ⅱ仿真验证(With the Verilog HDL language HDB3 coding, and simulation by Quartus Ⅱ)

用verilog实现sobel边缘检测算法(sobel edge detection with verilog language)

800 x 480 / inch lcd

max plus的入门与应用，适合初学者对max plus ii有一个感性的认识(max plus entry and applications, suitable for beginners to the max plus ii have a perceptual awareness of)

说明：  fpga程序，产生1pps脉冲信号，使用的verilog语言。(FPGA program generates 1 PPS pulse signal, using Verilog language.)

verilog 写的 “梁祝”乐曲演奏电路-verilog wrote " The Butterfly Lovers" music concert circuit

基于SDRAM的PCI采集,上位机为VC编写，桥芯片为PLX9054，项目已经做完，上传5个例程，已经验证通过(SDRAM, PCI-based acquisition, PC for VC preparation, bridge chip for PLX9054, the project has been done, upload 5 routines, has been verified by)

在八位七段数码显示管上显示8位学号，要显示的学号可以在程序内改，经设备验证无错误，且运行良好。

VHDL 基于cpld EPM570的DA转换代码(VHDL CPLD EPM570 the DA conversion code based on)