multiDDC

rs编码vvhdl 希望能通过 我不晓得具体对大家有用否 希望懂rs编码的多多交流 -rs coding vvhdl I do not want to be able to know the specific useful whether you want to understand a lot of coding rs exchange

processor design istruction load pipeline ,hazard

使用verliog设计实现LUT查找表乘法器，通过modelsim仿真验证通过(Designed and implemented using the LUT lookup table verliog multipliers, through simulation by modelsim)

基于FPGA的图像压缩算法程序，自己写的，可以参考一下(FPGA-based image compression algorithm, write your own, you can refer to)

基于Verilog HDL出租车计费系统的研制(Based on Verilog HDL Taxi Accounting System)

串口通讯，与硬件联通调试过，收发程序是分开的。(Serial Communication)

LATTICE FPGA FIFO 程序例程，工程详细，全部源代码上传 (LATTICE FPGA FIFO routine, detailed engineering, all source code uploaded)

cpld 控制 8-32M sdram 控制器 maxII epm570实现。 pdf 的说明文件-CPLD control 8-32M sdram controller maxII epm570 realize. pdf documentation

VHDL代码完成行列交织与解交织的功能实现(the realization of interleaver on VHDL language)

基于FPGA的任意波形信号发生器,可实现频率、幅度、相位的调节，输出方波、正弦波、锯齿波(Arbitrary waveform generator based on FPGA)