iic总线基于Verilog的实现

An Alarm Project Writen in VHDL for FPGA Devices

《FPGA数字信号处理与工程应用实践附光盘》配套源代码(FPGA DSP and their applications with verilog HDL)

rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)

自己写的 AXI slaver  verilog code，希望带给大家一些启示

Verilog HDL 语言编写的（15，7,2）BCH编码和译码功能(Verilog HDL language (15,7,2) BCH encoding and decoding functions)

A Dec example written in VHDL.

5阶数字滤波器 使用了coregenerator产生的multiplier，这个应该是最节省资源的方式了

RS编码是一种纠错码，本程序实现RS（255，223）用FPGA 实现RS编码，程序在Quartus II中调试通过。(RS coding is an error-correcting codes, the procedures for the realization of RS (255,223) with FPGA realization of RS codes, in the Quartus II program through the debugger.)

一个关于跨越异步时钟边界传输数据的解决方案(The solution of transfering data across asynchronous clock boundary.)

用三个按键控制pwm输出 key0控制是选着显示/改变频率或占空比 key1控制增加 key2控制减少 数码管显示频率或占空比 频率单位默认Hz（500-20KHz） 占空比范围（0.1-0.9）(Control PWM output with three keys Key0 controls display/change frequency or duty cycle optionally Key1 controls the increase Key2 controls are reduced Digital tube display frequency or duty ratio Frequency unit default Hz (500-20khz) Duty cycle range (0.1-0.9))