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dot_product
实现矩阵相乘,即点积运算,为VERILOG语言。可以根据自己的需要改变维数,采用了流水线的结构(Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure)
- 2015-01-27 10:52:52下载
- 积分:1
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uart
串口通信通用模块,FPGA Verilog语言 ise,vivado环境(uart,FPGA Verilog, ise,vivado)
- 2020-06-22 07:20:01下载
- 积分:1
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adding
加法器,输入两个整数,用电路图形式将其逻辑原理呈现出来,该加法器为8位运算,每一位都对应一张电路图,可展示其完整过程(Adder, input two integer, with circuit diagram form its logical principle appear, this adder is 8 bit arithmetic, each corresponding to a circuit diagram, can show the complete process)
- 2012-11-19 13:54:32下载
- 积分:1
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bp
说明: 基于BP算法的LDPC译码程序,采用vhdl语言,bp算法(BP algorithm based on LDPC decoding program using vhdl language, bp algorithm)
- 2016-04-12 16:59:55下载
- 积分:1
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HART-HT2015
HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号,在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯,数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)
- 2013-07-16 17:23:16下载
- 积分:1
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16QAM
16QAM调制解调程序画出时域波形、 正交分量、同相分量波形,眼图,散点图等(16QAM modulation and demodulation process to draw time-domain waveform, quadrature components, in-phase component waveforms, eye diagrams, scatter plots, etc.)
- 2013-06-04 22:10:41下载
- 积分:1
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Verilog乒乓操作实现的代码
利用verilog实现乒乓双缓存代码,比异步FIFO更可靠地缓存。
- 2022-02-26 23:38:45下载
- 积分:1
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xapp585
LVDS并行数据传输,来自XILINX官网(LVDS Parallel Data Transfer)
- 2020-06-29 08:20:02下载
- 积分:1
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fpga-fft
xlinx fpga实现fft功能,利用ip核,包含源程序及完整工程文件,直接就能使用(The fft function xlinx fpga ip-core contains the source code and complete the project file, and can be used directly)
- 2013-02-22 10:37:47下载
- 积分:1
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xj2
基于FPGA,利用VHDL语言对小车循迹进行设计。(Car tracking)
- 2011-11-01 22:36:25下载
- 积分:1