verilog编写的状态机检测00100序列. 实现 input:...011000010010000... output:...0000000001...

获取主机CPU信息，VS2008编译通过，含详细说明(Get information on the host CPU, VS2008 compiler, containing detailed instructions)

一种基于FPGA的通用微处理器设计-A general-purpose FPGA-based microprocessor designs ....

使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。(Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision)

利用VHDL语言设计一个分频器，输入为CLK,输出分别为CLK1、CLK8、CLK256、 CLK1024-The use of VHDL language design a divider, input CLK, the output respectively, CLK1, CLK8, CLK256, CLK1024

Hynix公司8M byte sdr sdram的verilog语言仿真实现。-Hynix company 8M byte sdr sdram realize the Verilog simulation language.

由VHDL 语言实现的D触发器利用的是QUARTUES环境已经得到验证-By the VHDL language using the D flip-flop is QUARTUES environment has been tested

Verilog语言编写的电话计费系统，这只是源代码，需要在quartusII等软件下运用-Verilog language telephone billing system, this is only the source code, the need to use software such as quartusII

包含一个ALU，实现斐波那契数列的计算。1.接受两个6位二进制输入。2.通过手动输入的时钟驱动每个周期进行一次计算。3.结果输出到led灯（使用NEXYS4开发板）(Including an ALU to realize the calculation of Fibonacci sequence. 1. Accept two 6-bit binary inputs. 2. Each cycle is driven by a clock input manually. 3. Output to LED lamp (using NEXYS4 development board))

本程序是用vhdl开发的实现并串转换功能的程序。(This procedure is developed using VHDL implementation and string conversion function of the program.)

Kluwer academic the verilog hardware description language fith edition