数字钟的VHDL源程序，可以实现在学校、年级的壮举…

USB 1.1 PHY的代码，systemc语言 USB 1.1 PHY的代码，systemc语言,包括基于systemc语言的testbench ，和相关的doc文档-USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents

七段数码管显示的时钟程序VHDL代码 ISE编译环境(SEVEN seg VHDL ISE CLOCK)

一个简单的移位寄存器。VHDL语言的，或许会对你有所帮助！-A simple shift register. VHDL language, and perhaps will help you!

Matlab agc ʵ

多人抢答器 源代码 实用 课程设计 用用VHDL语言-The source code for more than Responder practical courses designed for use with the VHDL language

一个电子中的verilog实验源代码。适合verilog初学者学习参考-an electronic experiments of Verilog source code. Suitable for beginners learning Verilog reference

LCD图形显示代码，已调试过，可以运行成功(LCD graphics display code has been debugged, you can run successfully)

verilog coding for butterworth filter with cut off frequency with 500hz

用FPGA于32进行SPI单向通信，FPGA向32放松发送数据(One-way SPI communication is carried out in 32 with FPGA, and data is sent to 32 with ease by FPGA.)

数字波形存储器VHDL源码，基于Quartus II开发。-Digital waveform memory VHDL source code, based on the Quartus II development.