数字钟的VHDL源程序，可以实现在学校、年级的壮举…

用verilog编写在FLEX10K上实现的简易CPU-used in the preparation of Verilog FLEX10K achieve simple CPU

运用VC编程的带LCD显示的信号发生器可用三个开个调节输出三个波形(Signal generator can be used three to open a regulator output waveform using VC programming with LCD display)

海德汉绝对式编码器代码，VHDL语言编写(Heidenhain absolute encoder code, VHDL language)

说明：  发送两个频段的脉冲 个数和频率均可调 发送两个频段的脉冲 个数和频率均可调(pluse and adjust the width of pluse pluse and adjust the width of pluse )

Fonts for LCD 162x64 (6x8)

c54x的VeriLog程序代码 也是opencoreip-C54x is the Verilog code opencoreip

ANALYSIS OF ALL GATESS

说明：  编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法(Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange)

802.11a Transmitter implementation Using Verilog

本文为verilog的源代码-In this paper, the source code for Verilog