RS码译码器

本例介绍直接合成带阻滤波器的方法，n阶滤波器能实现n个传输零点(A direct synthesis technique of a new class of bandstop coupled resonator elliptic filters is presented. Two different coupling schemes, which both include source–load coupling are used. The first coupling and routing scheme is the standard folded structure used in implementing bandpass elliptic filters with transmission zeros using resonators.)

八位并行数据转换为串行数据依时钟信号串行输出(Eight bit parallel data to serial data)

verilog编写的ds18b20温度传感器程序，可综合(ds18b20 program written in verilog)

xilinx公司提供的关于FPGA硬件设计的额时序约束参考资料-xilinx provided on the FPGA hardware design timing constraints of the amount of reference material

8051内核的Verilog程序实现，完成普通的单片机8051内核功能.包含综合后文件和测试文件(The 8051 kernel Verilog program complete ordinary microcontroller 8051 kernel function. Contains comprehensive post files and test files)

基于VHDL的I2C程序0003,很不错的论文及程序，，大家快下啊-based on the I2C procedures VHDL 0003, a very good paper and procedures, we quickly under ah

making a simple clock using altera vhdl

用verilog写的卷积码的编码程序以及viterbi译码程序(Use verilog write convolution code coding procedures and viterbi decoding program)

完整的TPC编译码VHDL程序，直接就可以运行(TPC encoder and decoder)

工具；