RS码译码器

说明：  使用verilog语言实现H.265压缩算法，能够实现实时视频数据的压缩传输(Using Verilog language to realize h.265 compression algorithm can realize the compression and transmission of real-time video data)

说明：  adc采集多路采集多通道基于dma的adc采集(ADC acquisition, multi-channel acquisition and multi-channel acquisition)

Viterbi译码器的编解码器的设计 用Verilog实现-Viterbi decoder。Verilog

xilinx FPGA设计需要的DDR2文件，可以应用于实际设计中(xilinx FPGA design needs DDR2 files that can be applied to the actual design)

高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format

基于TCAM的高速路由查找，逻辑实现深度为32的内容查找，得到索引和命中指示(TCAM lookup based on a high-speed routing logic to realize the depth of content to find 32, get indexed and hit instructions)

计数器是数字系统中使用最多的时序电路，它不仅能用于对时钟脉冲计数，还可以用于分频、定时、产生节拍脉冲和脉冲序列以及进行数字运算等。(Counter is the most frequently used sequential circuit in digital system. It can be used not only for counting clock pulses, but also for frequency division, timing, generating beat pulses and pulse sequences, and performing digital operations.)

The term web server can refer to either the hardware (the computer) or the software (the computer application) that helps to deliver web content that can be accessed through the Internet.(web server)

基于FPGA的Sobel边缘检测算法的实现与仿真。此程序提供算法的verliog实现。(Implementation and Simulation of Sobel edge detection algorithm based on FPGA. This program provides the verliog implementation of the algorithm.)

此压缩包里面有基于vivado平台的工程，包括了正弦信号的产生，还有fir滤波器的设计以及fft算法的设计实现(in this package,there are three projects of the generation of the signal of sin and the design of fir filter and the ari)