RS码译码器

A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.

一个基于fpga的源程序，对于初始接住的人来说很有帮助-FPGA-based source for the initial very helpful for those who catch

thesis about design and implementation neural network using FPGA

multisim 程序 使用教程 详细明了清楚(multisim tutorial program uses more clearly understand)

VHDL语言编写的FIR滤波器源码 对于嵌入式设计者有很好的指导作用 -VHDL prepared by the FIR filter source for Embedded designers have a good role in guiding

利用VHDL语言实现8位到32位的双向数据转换-use VHDL 8-32 two-way data conversion

说明：  APPCM算法和AD/DA芯片驱动在CPLD中的实现，已在实际硬件中测试OK，quartus2环境(APPCM algorithm and AD/DA chip in the drive to achieve in the CPLD has been tested in actual hardware OK, quartus2 environment)

说明：  现在最流行的RTL设计方法之一，本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)

用verilog 语言实现七人投票表决器(verilog seven voting)

入门，verilog语言，实现字符型液晶1602的显示，及按键控制-verilog