FPGA

mdct, it contains DOC,MATLAB,source,synthesis.

STOPWATCH FPGA SEVEN SEGMENT DISPLAY

该代码是基于verilog 实现的代码，可以用于对接受1080P的LVDS视频数据并处理后显示到各种规格的LCD屏幕上，且支持从FLASH中读取BMP的图片数据并实时显示到LCS屏幕(The code is based on the code verilog achieve, it can be used for receiving LVDS 1080P video and data processing displayed on a variety of LCD screen, and support for reading data the FLASH BMP images and real-time display to the LCS screen)

软件环境：TI的zstack协议栈 硬件：CC2530无线单片机 功能：利用超声波模块实现测距（该模块型号：HC-SR04 在淘宝上非常常见） 可测2厘米到3米距离(Software environment: TI' s zstack protocol stack hardware: CC2530 wireless microcontroller features: use of ultrasonic ranging module (the module Model: HC-SR04 on Taobao very common) can be measured 2 cm to 3 meters)

8路视频光端机 接收侧 VHDL源码，使用了千兆以太网SERDES芯片，基于TBI接口的PCM视频传输。-8-Channel Video Optical Receiver side of VHDL source code, using the Gigabit Ethernet SERDES chip, based on the TBI interface PCM video transmission.

这是“状态机设计（讲稿）”，希望对正在学VHDL的同学有帮助，谢谢！-This is the "state machine design (the script)", and I hope to learn VHDL is there to help the students, thank you!

说明：  实现UDP的网络传输，在PC建立UDP的服务器，向fpga的ip：192.168.0.25发送数据，实现回环通讯。(The network transmission of UDP is realized. UDP server is set up in PC, and the data is sent to IP: 192.168.0.25 of FPGA to realize loop communication.)

用于实现FPGA硬件开发使用的加法器，需要注意的是用Verilog语言实现的(The adder used to realize FPGA hardware development needs to be realized in Verilog language)

简单介绍了直接数字频率合成技术(DD S)，利用DDS设计任意 波形发生器，其能够产生矩形波、正弦波、三角波、锯齿波等多种波形 -A brief introduction of direct digital frequency synthesis (DD S), the use of DDS design of arbitrary waveform generator, which can produce rectangular wave, sine wave, triangle wave, sawtooth waveform etc.

mico8  vhdl  project lattice出的小资源mcu 256luts  值得学习