FPGA

用VHDL实现视频控制程序,实现对图像的采集和压缩,-Using VHDL realize video control procedures, to achieve image acquisition and compression,

verilog编写的基于CA算法的m序列发生器，其中验证了多种CA系数来实现m序列。(CA-based algorithm written in verilog m-sequence generator, which verify the CA factor to achieve a variety of m-sequence.)

it performs the floating point arithmetic unit

使用FPGA测量频率大小，并且在数码管上进行显示(Frequency measurement using FPGA and display on digital tube)

说明：  单周期cpu，使用verilog编写的的单周期cpu支持......等功能(Single cycle CPU, using Verilog written single cycle CPU support... And other functions)

ADS7844 AD转换芯片的VHDL控制器-ADS7844 AD converter chip VHDL controller

DE2-70,NIOS reference file,

verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be

msk比特误码率matlab仿真 匹配滤波器(the msk bit error rate matlab simulation matched filter)

DDR3控制器源码，针对XilinxFPGA的DDR3控制器的源码，已经验证通过。(DDR3 Controller，complete DDR3 controll，have pass verificaion.)