交通信号灯 Verilog 硬件实现

verilog，FPGA的TDC电路设计(verilog ，TDC base on FPGA)

说明：  FPGA实现PLL锁相环，输出不同频率的时钟控制信号。(FPGA realizes PLL and outputs clock control signals of different frequencies.)

完整的Verilog验证模型，包括设备完整的状态。(Complete verilog Verification Model)

关于FFT实现的Verilog代码，(FFT realize on the Verilog code,)

基于xilinx spartan 3E开发板，通过旋转编码器实现流水灯的左右移动闪烁变换。(Based on the Xilinx Spartan 3E development board, the left and right flicker transformation of the flow lamp is realized by the rotary encoder.)

时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。 OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system. OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)

fpga实现的IIC通信的例程，注释很详细(fpga implementation of serial communication routines, comments in great detail)

// 4 entry deep fast fifo module fifo4(clk, rst, clr,  din, we, dout, re, full, empty); parameter dw = 8; input clk, rst; input clr; input   [dw:1] din; input we; output  [dw:1] dout; input re; output full, empty; //////////////////////////////////////////////////////////////////// // // Local Wires // reg     [dw:1] mem[0:3]; reg     [1:0]   wp; reg     [1:0]   rp; wire    [1:0]   wp_p1; wire    [1:0]   wp_p2; wire    [1:0]   rp_p1; wire full, empty; reg gb; ///////////////////////////////////

将串行数据转换为并行的 Verilog 代码。从 rs232 端口的 8 位串行数据转换为 8 位并行数据。

该部分实现了百兆MAC的数据的收发功能，可直接连接MII接口的PHY芯片，进行通信，设计是基于国半的DP83849双口PHY进行开发，并进行过大量实例测试；应用中有问题可随时联系