rs(7,3)verilog编码

quartus 的220model 与 altera mf的库 用于fpga的modelsim仿真过程中添加到工程里面(the libary of 220 model and altera mf when we simulate the fpga project by modelsim)

VERILOG比较器设计，属于数字电子技术实验入门的资料。

spi driver: Analog Device DAC ad9788 SPI Controller

EKG SIGNAL PROCESSING THROUGH CORDIC

采用Quartus2编写的电子秒表电路 实现计时、暂停等功能(Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions)

quartus 17.1 安装包，我现在用的就是(Quartus 17.1 installation kit, what I am using now is)

xilinx 平台的SPI从接口实现源码，供参考学习(used xilinx,slave-spi interface.)

我写的源代码

说明：  这是8位CPU的CVDL代码。CPU 的主要功能是执行指令，控制完成计算机的各项操作，包括运算操作、传送操作、输入/输出操作等。作为模型计算机设计，将重点放在寄存器级，采取较简单的组成模式，以尽量简洁的设计帮助学生掌握CPU 的基本原理。 此次设计CPU就是为了了解CPU运行的原理，从而完成从指令系统到CPU的设计，并且通过仿真对CPU设计进行正确性评定。(The main function of CPU is to execute instructions, control and complete various operations of computer, including operation, transfer operation, input / output operation, etc. As a model computer design, it focuses on register level and adopts a simpler composition mode to help students master the basic principles of CPU with a concise design as far as possible. This design of CPU is to understand the principle of CPU operation, so as to complete the design from instruction system to CPU, and evaluate the correctness of CPU design through simulation.)

说明：  vhdl常见小实验代码，包括二进制比较器，4选1,8421十进制，8421转化成格雷码，8421余三码，分频器，数据码译码器，二进制减计数器，四位环形计数器等(VHDL common small experiment code)