UART的FPGA代码

spwm dcac逆变 fpga与单片机一起作用(sdad)

实现电梯的相关控制系统，在开发板EGO1上实现，数码管显示相关的楼层和状态(dianti in verilog)

MBD-FPGA数字滤波器设计基本流程,基于DSP builder(MBD-FPGA basic process of digital filter design)

利用FPGA开发板的PCIE接口实现数据的传输和发送。(Using the PCIE interface of FPGA development board to realize data transmission and transmission.)

7个发光二极管依次一个一个的时间显示，代码是用verilog编写的，是对艾伯特V2斯巴达板验证。

我们已在 verilog （硬件描述语言） 实施 D 触发器。该代码被合成模拟在 Xilinx ISE 设计套件 14。

实现相机采集数据的自动白平衡功能，采用verilog语言编写。(The automatic white balance function of camera data acquisition is realized)

1、用状态机设计A/D转换器ADC0809的采样控制电路，并在数码管上显示转换结果； 2、设置有复位和启动/保持开关，要求 ⑴ 复位开关用来使A/D转换器复位，并做好A/D转换准备； ⑵ 启动/保持开关用来控制A/D转换器开始连续转换或停止转换保持结果，即按一下启动/保持开关，启动A/D转换器开始转换，再按一下启/停开关，停止转换并保持结果。 3、采用Verilog HDL语言设计符合上述功能要求的控制电路。(1, with the state machine design A/D converter ADC0809 sampling control circuit and display the results on the digital conversion 2 is provided with a reset and start/hold switch, reset switch is used to make the request ⑴ A/D converter reset and do A/D conversion ready ⑵ start/hold switch is used to control the A/D converter starts converting or stop the conversion to maintain a continuous result that by clicking Start/hold switch, start the A/D converter to start the conversion, and then Click the start/stop switch stops the conversion and keep the results. 3, using Verilog HDL language designed to meet the functional requirements of the above-mentioned control circuit.)

不足20元的PCI设计，含ABEL源代码。(PCI design less than 20Yuan ,including ABEL code)

Description of a sistolic arhictecture for a FFT implementation in FPGA.