设计采用Verilog自动贩卖机实施

FPGA 帧同步源代码 调试无错误 ALTERA 平台(Frame synchronization FPGA)

dds 频率可控，32位 输出为12位 已含有.hex文件，直接装载致ROM即可~(dds frequency-controlled, 32-bit output is 12 already contains. hex file can be loaded directly caused ROM ~)

说明：  This is code of UVM CALLBACK function.

说明：  基于FPGA的芯片信号发生器，利用Verilog语言实现信号发生器的各个模块单元， 实现的要求：正弦波、三角波、方波等；(Based on FPGA chip signal generator, using Verilog language to realize each module unit of the signal generator, Requirements: sine wave, triangle wave, square wave, etc;)

基于Qsys的嵌入式软核设计，基于Quartus的顶层模块设计，以及利用简单的C语言在nios2中实现花样灯的程序。实验的芯片是飓风二代，EP2C8Q208C8开发板。

说明：  异步VLSI大规模电路设计的圣经，一本很经典的异步电路入门书籍(The Bible of Asynchronous VLSI Large Scale Circuit Design, A Classic Introduction to Asynchronous Circuits)

DAC0832的Verilog代码，适用于与ADC0809同时学习，效果明显！(DAC0832 Verilog code, applicable at the same time with ADC0809 learning, the effect is obvious!)

SystemVerilog For Design (Springer-2nd_Ed-2006)

FPGA实现FSK调制，带Modelsim仿真，实际系统测试通过，载波信号，信号频率等可调。(FPGA implementation FSK modulation with Modelsim simulation, the actual system test, the carrier signal, the signal frequency is adjustable.)

基于FPGA，利用VHDL语言对小车循迹进行设计。(Car tracking)