设计采用Verilog自动贩卖机实施

说明：  经过验证的经典实例，完全正确的。适合于入门新手的实例，仅供交流使用。(fpga exampe)

开源的ULPI IP核，可用于USB3300芯片的开发(openSource ULPI IP core which could be used for USB3300 chip development)

说明：  通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic communication )

对用开发板上开关产生的信息做汉明编码并通过串口发送至电脑(The Hamming code is generated from the switch on the development board and sent to the computer through the serial port.)

基于quartus的布斯乘法器的verilog 实现。布斯乘法算法是计算机中一种利用数的2的补码形式来计算乘法的算法。该算法由安德鲁·唐纳德·布斯于1950 年发明，当时他在伦敦大学伯克贝克学院做晶体学研究。布斯曾使用过台式计算器，由于用这种计算器来做移位计算比加法快，他发明了该算法来加快计算速度。(The verilog codes of booth multiplier based on quartus. Booth multiplication algorithm is a computer algorithm using the complement form of number 2 to calculate the multiplication. The algorithm was invented in 1950 by Andrew Donald booth, who was working on crystallography at birkbeck college, university of London. Booth used a desktop calculator, and because it was faster to do shifts than to add, he invented the algorithm to speed up the calculations.)

cordic 算法知道正弦和余弦值，求反正切，即角度。(The CORDIC algorithm knows sine and cosine values and asks for inverse tangent, that is, angle.)

Decimation-In-Time Fast Fourier Transform I"ve tried to make the implementation simple and well documented. I have not tried to make it efficient. dit.v - Contains main module. buffer.v - Contains a module for a single butterfly step. generate_twiddlefactors.py - Contains function to generate a verilog file with twiddlefactors. twiddlefactors_N.v.t - Template used to generate verilog file. dut_dit.v - A wrapper around the "dit" module to allow verification with MyHDL. qa_dit.py - A MyHDL test bench for verification. Requires MyHDL, iverilog and numpy to be installed. pyfft.py - Generates output of intermediate FFT stages. Useful for debugging.

verilog实现RTC功能，可直接用于芯片开发中。(verilog achieve RTC function can be directly used for chip development.)

利用Verilog实现了二维卷积的操作，输入特征图尺寸为7x7，卷积核尺寸为5x5，分别使用了折叠、脉动阵列行固定、脉动阵列权重保持三种硬件实现设计方法来完成二维卷积的设计。

圖形介面乘法器,也可自行使用verilog去改(Graphical interface multiplier, also free to use verilog go and change)