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adder_array
adder_array的设计。加法器阵列设计,顶层模块,四步流水,21位(adder_array the design. The adder array design, top-level module, four-step pipeline, 21)
- 2013-04-17 00:19:05下载
- 积分:1
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Xilinx ISE 8.2i s license
Xilinx ISE 8.2i的license-Xilinx ISE 8.2i s license
- 2023-06-08 10:45:03下载
- 积分:1
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20081209_Test_maus
Its project to move your mouse cursor on a vga monitor. it is very funny -)(Its project to move your mouse cursor on a vga monitor. it is very funny -))
- 2009-05-12 18:53:12下载
- 积分:1
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EDA
EDA技术及其应用《序列信号发生器的设计》,包括源文件。(EDA technology and its applications " sequence signal generator design, including source files.)
- 2012-10-29 18:30:40下载
- 积分:1
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DE2_CCD
说明: 此程序用来实现图像的采集和帧数的计算功能。(Image acquisition and calculation of the number of frames.)
- 2011-04-17 09:43:37下载
- 积分:1
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这篇文章主要是概要的阐述了如何使用
这篇文章主要是概要的阐述了如何使用-quartusⅡ+Modelsim+synplify pro,来设计FPGA系统。-This is a summary of the main article on how to use the-quartus Ⅱ+ Modelsim+ synplify pro, to design FPGA systems.
- 2022-01-26 08:00:21下载
- 积分:1
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8051corelcd
fpga上实现的51内核,带有LCD试验,顺利试验成功很好用。(on fpga implementation of 51 core with LCD test, successfully tested well with the smooth.)
- 2014-03-30 14:35:20下载
- 积分:1
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基于EPM1270的VGA显示器接口源码Verilog
基于EPM1270的VGA显示器接口源码Verilog-Based on the EPM1270
- 2022-03-24 16:21:09下载
- 积分:1
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sdcard_mass_storage_controller
A host controlled ot control sd cards
- 2021-04-29 13:58:43下载
- 积分:1
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ISE7.1,采用VIRTEX
ISE7.1,采用VIRTEX-II芯片。实现adc数据采样,平均,通道选择,采样时钟选择,数据格式调整,内含fifo,uart等模块。-ISE7.1, using VIRTEX-II chip. Adc realize data sampling, on average, channel selection, the sampling clock select, adjust data formats, including fifo, uart modules.
- 2022-03-28 19:34:46下载
- 积分:1