基于FPGA的数字钟

实现了三种乘法器，可以进行性能比较，比较有较之-multi

目前最新的OVL库，里面是标准的ASSERTION模块，支持VHDL刚Verilog，最近在做AXI协议验证的时候用到，分享下(The latest OVL(open verification library),including all standard module of assertions(VHDL and Verilog). It can be used into AXI Protocl Verification. Just share with you guys.)

PC104总线的CPLD代码，调试已经通过，可以修改应用到其他的工程(PC104 bus CPLD code, debugging has been passed, you can modify the application to other engineering 示例用法:)

FPGA KIT DE2-35 This project outputs a selected voltaje using VGA DAC, the DAC module is controlled using LCD display and buttons.

AD768产生锯齿波的源码，DA转化的最基本操作。(AD768 sawtooth source code, the basic operation of DA conversion.)

《Verilog HDL 程序设计教程》3-"Verilog HDL Design Guide" 3

对pci9054芯片的配置进行了设置，并对PCI9054的各状态机进行了设置，程序经过了测试(Pci9054 chip on the configuration of the set, and each state machine PCI9054 been set, the program have been tested)

这是一个EOS项目中的GFP成帧结构，能够容错，可以配置字节域(This is an EOS project GFP Framing structure, be able to fault-tolerant, can be configured byte domain)

通过数码管和单片机的组合 制作成的数码管时钟程序(Through the combination of digital control and made ​ ​ into a single-chip digital clock program)

HDL example source code 1/5 dff_as