《Verilog HDL 程序设计教程》3

verilog实现UART收发功能，硬件平台为spartan 6，软件平台为ise14.7(verilog implement UART rx and tx function)

主要用来介绍如何编写高质量的verilog程序的(Is mainly used to describes how to write high-quality verilog programs)

拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现(Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone)

i2c master ip for altera nios, add in qsys

VerilogHDL.自动增益控制模块中产生控制电压的部分-VerilogHDL. Automatic Gain Control Module have some control voltage

Syllabus for VSC-HVDC course

OFDM modulation source code written in Matlab

stepper motor module on spartan 6 and 24MHz clock fequency

A program for a simple decoder using ModelSim6

此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16(this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY)