《Verilog HDL 程序设计教程》3

此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)

pcf8563，在quartusII下VERILOG编写的数字时钟程序，8位数码管显示(pcf8563, written in quartusII VERILOG digital clock program, eight digital display)

This is an UART real time clock

用MSP430进行压力测试，完成数据的分析(with msp430 to continue on press test.to complete about the anlysys about data)

从MIC输入一段音频然后，再从AOUT的接口播放出来的verilog 的代码-Input from the MIC for some audio and then AOUT interface from broadcast in the Verilog code

一个关于跨越异步时钟边界传输数据的解决方案(The solution of transfering data across asynchronous clock boundary.)

关于数字电压表的vhdl实现，有仿真程序，可以下载到板子中。(Vhdl digital voltage meter on the implementation of a simulation program can be downloaded to the board.)

CycloneIV控制采样芯片AD9248-20MHz，VHDL语言(CycloneIV control sampling chip AD9248-20MHz, VHDL language)

这是篇<基于FPGA 的OFDM 宽带数据通信同步系统设计与实现>, 觉得甚是有用，大家共同学学。(This is the article <FPGA-OFDM-based broadband data communication systems design and implementation of synchronous> that even be useful, we all learn together.)

说明：  计算机组成原理实验多时钟周期CPU设计，包含VHDL代码的设计，实验电路图，实验详细截图。(Computer component experiments designed more CPU clock cycles, including VHDL code design, test circuit, test detailed screenshots.)