《Verilog HDL 程序设计教程》3

USB 1.1 PHY的代码，systemc语言 USB 1.1 PHY的代码，systemc语言,包括基于systemc语言的testbench ，和相关的doc文档-USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents

xilinx提供的频率发生器的VHDL源码，可以运行在spartan3的学习开发板上。-xilinx the frequency generator VHDL source code, spartan3 can run in the learning development board.

资源描述该乘法器可用于过滤器，算术运算和；

MP3解码的ASIC全部过程，包换含c和vhdl代码，样例。(MP3 decoding ASIC whole process, shifting with c and vhdl code, sample.)

it performs the floating point arithmetic unit

采用VHDL编写的频率计，模块划分清晰易懂，基本原理为检测一个闸门脉冲周期内的信号次数，采用四段数码管显示

用于单片机的adc采集实验，经过降噪处理，结果精确(ADC acquisition experiment for single chip computer, after noise reduction processing, the result is accurate)

verilog 键盘输入程序，用于led灯的显示-Verilog keyboard input program for led lights display

FIFO程序，适用FPGA仿真的代码，有一定的价值-FIFO

三相PWM整流，实现功率双向流动,可保持直流侧电压稳定(three-phase PWM rectifier, power can bidirectional flow ，can maintain the stable DC voltage)