用CPLD驱动扬声器实现音乐的播放，程序是用VERILOG写的，

实现基于FPGA的vga显示，亲测能编译得过，不同开发版应该要相应改动（PS: 不太了解）

modelsim下的60进制计数器源码和测试激励文件(modelsim M counter 60 under the source file and test incentives)

24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.

简易信号波形发生器，可以产生四种波形，频率1k-20K步进可调。学习Verilog HDL的好例子。(imple signal waveform generator, can produce four waveform, frequency 1 k-20 k step can be adjusted. Learning Verilog good example of HDL. )

verilog编写的16阶升余弦滤波器 采用直接型结构实现 对方波进行滤波 输出波形 含testbench文件(order raised cosine filter verilog written 16 direct-type structure to achieve the other wave filtering the output waveform containing testbench file)

一本很好的教程，适合初学者,里面有详细的教程，很值得一看！！(A good tutorial, suitable for beginners, there are detailed tutorials, it is worth a visit!!)

内有LED译码器，汉明纠错译码器，地址译码器，最高优先译码器，双2－4译码器等VHDL的源代码-decoder, Hamming error correction decoder, address decoder, the highest priority decoder, dual 2-4 decoder such as VHDL source code

实现了从摄像头读取数据到液晶的显示，利用了cycloneV 和康欣的开发板资源(It realizes the display of reading data from camera to liquid crystal.)

CMV2000的对齐模块，适用于其他对齐模块，自行修改(CMV2000 alignment module, suitable for other alignment modules, self-modifying)

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE