用CPLD驱动扬声器实现音乐的播放，程序是用VERILOG写的，

FPGA的SRAM存储器的控制程序，包括时序测试-FPGA

本设计是基于EP4CE15F17C8N和12864液晶的频率计程序(The design is based EP4CE15F17C8N and 12864 LCD frequency meter program)

说明：  Matlab源程序，包括插值计算、积分微分等。(Matlab source code, including the interpolation calculations, differential and so on.)

System Verilog decodificator. Enters a value(binary), drops hundreds, tens and units in BCD

内容太短。注意请： 代码没有很好的描述将被删除，你不会得到任何点。请描述一下更好地获得更多积分。

SPARC Assembly Language Reference Manual

使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路(Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas)

Simple ALU Objectives 1. Explore simple ALU structure. 2. Working with components 3. Working with language templates in ModelSim 4. Making a test bench and simulation using ModelSim

DDS实验 matlab 与quartus 的完美结合(DDS experimental combination of matlab and quartus)

基于VHDL+FPGA的神经网络设计，实现简单的字符识别(Design of Neural Network Based on VHDL+FPGA to Realize Simple Character Recognition)