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Stumper.cpp
Convert Roman numerals to integers
- 2012-12-05 03:59:59下载
- 积分：1
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Wishbone dma ip core
Wishbone dma ip core
- 2022-01-26 04:18:15下载
- 积分：1
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VHDL的寄存器读写参考，可自己根据要求重新修改，本示范只做参考用...
VHDL的寄存器读写参考，可自己根据要求重新修改，本示范只做参考用-Register read and write VHDL reference to their request to amend in accordance with, the reference model only
- 2022-09-23 06:45:03下载
- 积分：1
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pro1
对用开发板上开关产生的信息做汉明编码并通过串口发送至电脑(The Hamming code is generated from the switch on the development board and sent to the computer through the serial port.)
- 2018-11-15 17:01:21下载
- 积分：1
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am
基于FPGA的用verilog语言写的，改程序可产生不同调制系数和不同频率的AM波，长按按键切换调制度25 、50 、75 和短按按键切换调制信号频率1k、1.5k、2k、2.5k.(Based on the FPGA using verilog language, change the program can produce different coefficients and different frequency modulated AM wave, long press the button to switch the modulation of 25 , 50 , 75 and short press button to switch the modulation signal frequency 1k, 1.5k, 2k, 2.5k.)
- 2013-10-14 22:14:56下载
- 积分：1
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根据音乐发生的机理，将复杂可编程逻辑器件作为发生音乐的核心器件，用高速集成电路硬件描述语言编程描述发生的音乐乐谱，配合周边硬件电路，由电声转换发声器接收信号，从...
根据音乐发生的机理，将复杂可编程逻辑器件作为发生音乐的核心器件，用高速集成电路硬件描述语言编程描述发生的音乐乐谱，配合周边硬件电路，由电声转换发声器接收信号，从而发出音乐声，实验表明，采用该方法设计的音乐发生器成本低、修改方便-Music took place in accordance with the mechanism of complex programmable logic device, as occurred in the core of music devices, with high-speed integrated circuit hardware description language to describe the occurrence of music notation, with the peripheral hardware circuits, electro-acoustic conversion by the audible signal device to receive signals, which issued music, experiments show that this method of music generator design and low cost, easy to amend
- 2023-06-27 23:25:04下载
- 积分：1
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apb_uart
说明： 这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)
- 2021-04-12 14:18:57下载
- 积分：1
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detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system desi...
detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.
- 2022-04-24 22:44:35下载
- 积分：1
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COSTAS环载波同步
说明： how to come ture a costas loop in FPGA with verilog,it is very useful on project
- 2019-05-07 11:12:02下载
- 积分：1
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c8
说明： QPSK 调制 与 解调的源代码 可综合 出波形(QPSK modulation and demodulation of the source code)
- 2011-03-04 00:17:17下载
- 积分：1
